FPGA-based fault analysis for 7-level switched ladder multi-level inverter using decision tree algorithm

Abstract

The proposed method involves the fault analysis of the inverter switches present in the multi-level inverter (MLI) circuitry. The decision tree machine learning algorithm is incorporated for the fault analysis of the inverter switches. The multi-level inverter utilized in this work is a 7-level switched ladder multi-level inverter. There is 4 number of switches in the design of a 7-level inverter driven by the non-carrier digital pulse width modulation signals. The non-carried-based digital pulse-width modulator (DPWM) generation is generated using the event angle for the 7-level of the switched ladder inverter. The proposed method investigates the stuck-at-fault occurrences of the 4 switches in the inverter by manipulating the decision tree parameters such as entropy, information gain, and decision tree. Based on the decision tree, the very high-speed integrated circuit hardware description language (VHDL) code is developed by making use of the behavioral modeling and validated for the power, area in the Xilinx Vivado tool. The real-time feasibility is verified for the proposed method by synthesizing the developed VHDL code in the field programmable gate array (FPGA) device.

Implementation of first order statistical processor on FPGA for feature extraction

“…FPGAs have demonstrated their capability not only in fault analysis and circuitry but also in performing complex logic tasks such as neural network implementation and biomedical signal processing. In the fault analysis of multi-level inverters, FPGAs enable the incorporation of decision tree machine learning algorithms to analyze the inverter switches efficiently [24]. Moreover, FPGAs prove their suitability for implementing compact neural networks that replace extensive code in higher-level languages for estimating thermodynamic properties and their derivatives in real-time applications.…”