FPGA based architecture for DNA sequence comparison and database search

Sotiriades,; Kozanitis,; Dollas,

doi:10.1109/ipdps.2006.1639443

Cited by 28 publications

(19 citation statements)

References 11 publications

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“…In [36], [37], Sotiriades et al develop the first version of TUC BLAST in which the entire BLAST algorithm is mapped onto Virtex-4 4VFX140FF1517-11 FPGA. The architecture can support small queries of up to 1,000/ 5,000 letters regardless of the database size.…”

Section: B Database Searchmentioning

confidence: 99%

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Liu

Luk

2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Genetic sequence alignment has always been a computational challenge in bioinformatics. Depending on the problem size, software-based aligners can take multiple CPUdays to process the sequence data, creating a bottleneck point in bioinformatic analysis flow. Reconfigurable accelerator can achieve high performance for such computation by providing massive parallelism, but at the expense of programming flexibility and thus has not been commensurately used by practitioners. Therefore, this paper aims to provide a thorough survey of the proposed accelerators by giving a qualitative categorization based on their algorithms and speedup. A comprehensive comparison between work is also presented so as to guide selection for biologist, and to provide insight on future research direction for FPGA scientists.

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Section: B Database Searchmentioning

confidence: 99%

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Liu

Luk

2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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“…ATCHING large sets of patterns against an incoming stream of data is a fundamental task in several fields such as network security [1]- [12] or computational biology [13], [14]. For example, high-speed network intrusion detection systems (IDS) rely on efficient pattern matching techniques to analyze the packet payload and make decisions on the significance of the packet body.…”

mentioning

confidence: 99%

Scalable Multigigabit Pattern Matching for Packet Inspection

Sourdis

Pnevmatikatos

Vassiliadis

2008

IEEE Trans. VLSI Syst.

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Abstract-In this paper, we consider hardware-based scanning and analyzing packets payload in order to detect hazardous contents. We present two pattern matching techniques to compare incoming packets against intrusion detection search patterns. The first approach, decoded partial CAM (DpCAM), predecodes incoming characters, aligns the decoded data, and performs logical AND on them to produce the match signal for each pattern. The second approach, perfect hashing memory (PHmem), uses perfect hashing to determine a unique memory location that contains the search pattern and a comparison between incoming data and memory output to determine the match. Both techniques are well suited for reconfigurable logic and match about 2200 intrusion detection patterns using a single Virtex2 field-programmable gate-array device. We show that DpCAM achieves a throughput between 2 and 8 Gb/s requiring 0.58-2.57 logic cells per search character. On the other hand, PHmem designs can support 2-5.7 Gb/s using a few tens of block RAMs (630-1404 kb) and only 0.28-0.65 logic cells per character. We evaluate both approaches in terms of performance and area cost and analyze their efficiency, scalability, and tradeoffs. Finally, we show that our designs achieve at least 30% higher efficiency compared to previous work, measured in throughput per area required per search character.

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“…The capability in Multi-engine BLASTn Accelerator [16] achieves 6400M matches/s by using 64 identical parallel engines. Comparatively, our searching engine can execute 294912M word matches per second, over 40 times, by using the multi-seeds parallel detecting approach.…”

Section: Test 3: Comparing To Index-based Hardware Acceleratorsmentioning

confidence: 99%

“…Recently, FPGA chips have emerged as one promising application accelerator, using a combination of FPGAs and general-purpose CPUs to accelerate BLAST algorithm attracts much more attention. A number of parallel architectures have been proposed, such as Mercury BLASTn [8], [9], [10], Tree-BLAST [11], Mercury BLASTp [12], RC-BLAST [13], FPGA/FLASH Accelerator [14], Multiengine BLASTn Accelerator [15], [16] and many commercialized system, BEE2 [17], CLC Cube [18], Mitrion [19] and DeCypher [20] et al have been built.…”

Section: Introductionmentioning

confidence: 99%

“…The storage cost will be intolerable with the steep growth of database. To improve searching efficiency, Multi-engines BLASTn [16] fitted 64 identical computing machines in single chip to compare the query with 64 subject sequences in database concurrently and Mercury BLASTp [12] implemented a two-seed generator for accelerating the first stage of BLASTp. Unfortunately, these approaches are still based on the query index essentially.…”

Section: Introductionmentioning

confidence: 99%

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Families of FPGA-Based Accelerators for BLAST Algorithm with Multi-seeds Detection and Parallel Extension

Xia

Dou

Communications in Computer and Information Science

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Abstract. As one of the most widely used bio-sequence searching tools, BLAST adopts index-based approach to detect the matches between two substrings by looking up a large table and processing one match per query. In this paper, we propose a systolic array approach to detect string matches without using looking up tables. The pipelining systolic array is implemented as a multi-seeds detection and parallel extension pipeline engine to accelerate the first two stages of NCBI BLAST family algorithms. Different from the index-based approach, our implementation consumes little memory resources and eliminates redundant string extensions by merging multiple adjoin seeds into a valid seed. Our FPGA implementation achieves superior performance results in both of processing element number and clock frequency over related works in the area of FPGA BLAST accelerators. The experimental results also show the speedup can reach about 17, 48, 14, 71 and 10 compared to the NCBI BLASTp, TBLASTn, BLASTx, TBLASTx and BLASTn programs for 3072-residue queries on Intel P4 CPU, respectively. Furthermore, the idea of multi-seeds detection also can be adopted in other seed-based heuristic searching applications.

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FPGA based architecture for DNA sequence comparison and database search

Abstract: Abstract

Cited by 28 publications

References 11 publications

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Scalable Multigigabit Pattern Matching for Packet Inspection

Families of FPGA-Based Accelerators for BLAST Algorithm with Multi-seeds Detection and Parallel Extension

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