“…Several architectures for the computation of cryptographic pairings have been proposed in the literature [14,15,16,17,18,19,20,21,22,23,24,25,26]. All these implementations use supersingular curves over fields of characteristic 2 or 3, achieving only very low security levels, sometimes even below 80 bit.…”
Abstract. This paper presents a design-space exploration of an application-specific instruction-set processor (ASIP) for the computation of various cryptographic pairings over Barreto-Naehrig curves (BN curves). Cryptographic pairings are based on elliptic curves over finite fields-in the case of BN curves a field Fp of large prime order p. Efficient arithmetic in these fields is crucial for fast computation of pairings. Moreover, computation of cryptographic pairings is much more complex than elliptic-curve cryptography (ECC) in general. Therefore, we facilitate programming of the proposed ASIP by providing a C compiler.In order to speed up Fp arithmetic, a RISC core is extended with additional scalable functional units. Because the resulting speedup can be limited by the memory throughput, utilization of multiple data-memory banks is proposed.The presented design needs 15.8 ms for the computation of the Optimal-Ate pairing over a 256-bit BN curve at 338 MHz implemented with a 130 nm standard cell library. The processor core consumes 97 kGates making it suitable for the use in embedded systems.
“…Several architectures for the computation of cryptographic pairings have been proposed in the literature [14,15,16,17,18,19,20,21,22,23,24,25,26]. All these implementations use supersingular curves over fields of characteristic 2 or 3, achieving only very low security levels, sometimes even below 80 bit.…”
Abstract. This paper presents a design-space exploration of an application-specific instruction-set processor (ASIP) for the computation of various cryptographic pairings over Barreto-Naehrig curves (BN curves). Cryptographic pairings are based on elliptic curves over finite fields-in the case of BN curves a field Fp of large prime order p. Efficient arithmetic in these fields is crucial for fast computation of pairings. Moreover, computation of cryptographic pairings is much more complex than elliptic-curve cryptography (ECC) in general. Therefore, we facilitate programming of the proposed ASIP by providing a C compiler.In order to speed up Fp arithmetic, a RISC core is extended with additional scalable functional units. Because the resulting speedup can be limited by the memory throughput, utilization of multiple data-memory banks is proposed.The presented design needs 15.8 ms for the computation of the Optimal-Ate pairing over a 256-bit BN curve at 338 MHz implemented with a 130 nm standard cell library. The processor core consumes 97 kGates making it suitable for the use in embedded systems.
“…There are recent efforts on applying FPGAs as accelerators for parallel data analytics (Court et al, 2004;Ronan et al, 2006;Woods & VanCourt, 2008). Shan et.al present a framework to use FPGAs to accelerate MapReduce processing in (Shan et al, 2010).…”
Privacy is one of the critical concerns that hinders the adoption of public cloud. For simple application, like storage, encryption can be used to protect user's data. But for outsourced data processing, i.e., big data processing with MapReduce framework, there is no satisfying solution. Users have to trust the cloud service providers that they will not leak users' data. We propose adding black boxes to the public cloud for critical computation, which are tamper resistant to most adversaries. Specifically, FPGAs are deployed in the public cloud environment as black boxes for privacy preserving computation, and proxy re-encryption is used to support dynamic job scheduling on different FPGAs. In FPGA cloud, cloud is not necessarily fully trusted, and during outsourced computation, user's data is protected by a data encryption key only accessible by trusted FPGA devices. As an important application of cloud computing, we apply FPGA cloud to the popular MapReduce programming model and extend the FPGA based MapReduce pipeline with privacy protection capabilities. Finally, we conduct experiments and evaluation for k-NN with FPGA cloud, which is an important MapReduce application. The experimental results show the practicality of FPGA cloud.
“…There are recent efforts on applying FPGAs as accelerators for parallel data analytics (Court et al, 2004;Ronan et al, 2006;Woods & Van Court, 2008). Shan et.al present a framework to use FPGAs to accelerate MapReduce processing in (Shan et al, 2010).…”
Section: Related Workmentioning
confidence: 99%
“…FPGAs are considered to be powerful computation devices and suited as accelerators for b ig data analytics. It is common for many applications to employ FPGA based devices to accelerate their performance (e.g., (Court, Gu & Herbordt, 2004;Ronan, Éigeartaigh, Murphy, Scott & Kerins, 2006;Woods & VanCourt, 2008)). FPGAs are also deployed in the cloud environment as accelerators for large scale data processing such as MapReduce (Shan, Wang, Yan, Wang, Xu & Yang, 2010).…”
Privacy is one of the critical concerns that hinders the adoption of public cloud. For simple application, like storage, encryption can be used to protect user's data. But for outsourced data processing, i.e., big data processing with MapReduce framework, there is no satisfying solution. Users have to trust the cloud service providers that they will not leak users' data. We propose adding black boxes to the public cloud for critical computation, which are tamper resistant to mos t adversaries. Specifically, FPGAs are deployed in the public cloud environment as black boxes for privacy preserving computation, and proxy re-encryption is used to support dynamic job scheduling on different FPGAs. In FPGA cloud, cloud is not necessarily fully trusted, and during outsourced computation, us er's data is protected by a data encryption key only accessible by trusted FPGA devices. As an important application of cloud computi ng, we apply FPGA cloud to the popular MapReduce programmi ng model and extend the FPGA based MapReduce pi peline with privacy protection capabilities. Fi nally, we conduct experiments and evaluation for k-NN with FPGA cloud, which is an important M apReduce application. The experimental results show the practicality of FPGA cloud.
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