FPGA-Accelerated Molecular Dynamics

Khan, Md. Ashfaquzzaman; Chiu, Matt; Herbordt, Martin C.

doi:10.1007/978-1-4614-1791-0_4

Cited by 14 publications

(8 citation statements)

References 41 publications

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“…Most studies on FPGA accelerated MD target the PP calculations [10], [11], [13], [14], [20][21][22], since they make up for over 90% of the sequential runtime in typical simulations. Apart from these studies, only relatively few papers cover PME and other aspects [16], [18], [19], [45].…”

Section: MD Acceleration Using Fpgasmentioning

confidence: 99%

“…We note that most work in the area has been done by the group by M. Herbordt at Boston University, including the design of several variations of PP interaction pipelines [13], [14], [20], [21], [46] and a prototype where such a PP interaction pipeline is integrated into a simplified variant of NAMD [14]. Their PP interaction pipelines makes use of particle filters that build the neighborlists on-the-fly.…”

Section: MD Acceleration Using Fpgasmentioning

confidence: 99%

“…Besides these MPI and GPU-based solutions, FPGA accelerators have repeatedly been proposed as a viable alternative to accelerate the compute intensive parts [10][11][12][13][14][15][16][17][18][19][20][21][22] . However, these studies only show estimated or measured speedup with respect to older CPU implementations.…”

Section: Introductionmentioning

confidence: 99%

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On the Feasibility of FPGA Acceleration of Molecular Dynamics Simulations

Schaffner¹,

Benini²

2018

Preprint

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Classical molecular dynamics (MD) simulations are important tools in life and material sciences since they allow studying chemical and biological processes in detail. However, the inherent scalability problem of particle-particle interactions and the sequential dependency of subsequent time steps render MD computationally intensive and difficult to scale. To this end, specialized FPGA-based accelerators have been repeatedly proposed to ameliorate this problem. However, to date none of the leading MD simulation packages fully support FPGA acceleration and a direct comparison of GPU versus FPGA accelerated codes has remained elusive so far.With this report, we aim at clarifying this issue by comparing measured application performance on GPU-dense compute nodes with performance and cost estimates of a FPGA-based singlenode system. Our results show that an FPGA-based system can indeed outperform a similarly configured GPU-based system, but the overall application-level speedup remains in the order of 2× due to software overheads on the host. Considering the price for GPU and FPGA solutions, we observe that GPU-based solutions provide the better cost/performance tradeoff, and hence pure FPGA-based solutions are likely not going to be commercially viable. However, we also note that scaled multi-node systems could potentially benefit from a hybrid composition, where GPUs are used for compute intensive parts and FPGAs for latency and communication sensitive tasks.

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Section: MD Acceleration Using Fpgasmentioning

confidence: 99%

Section: MD Acceleration Using Fpgasmentioning

confidence: 99%

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On the Feasibility of FPGA Acceleration of Molecular Dynamics Simulations

Schaffner¹,

Benini²

2018

Preprint

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“…(Chiu et al, 2008;Chiu and Herbordt, 2009) (Herbordt, 2013) researched the approaches of the architecture/algorithm codesign of MD processors. (Herbordt et al, 2007;Herbordt et al, 2008;Khan et al, 2013;Vancourt and Herbordt, 2009) provide general overviews of these methods.…”

Section: Previous Work Of 3d Ffts On Fpgasmentioning

confidence: 99%

High Performance Communication on Reconfigurable Clusters

Sheng

Yang

Herbordt

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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High Performance Computing (HPC) has matured to where it is an essential third pillar, along with theory and experiment, in most domains of science and engineering. Communication latency is a key factor that is limiting the performance of HPC, but can be addressed by integrating communication into accelerators. This integration allows accelerators to communicate with each other without CPU interactions, and even bypassing the network stack. Field Programmable Gate Arrays (FPGAs) are the accelerators that currently best integrate communication with computation. The large number of Multi-gigabit Transceivers (MGTs) on most high-end FPGAs can provide high-bandwidth and low-latency inter-FPGA connections. Additionally, the reconfigurable FPGA fabric enables tight coupling between computation kernel and network interface. Our thesis is that an application-aware communication infrastructure for a multi-FPGA system makes substantial progress in solving the HPC communication bottleneck. This dissertation aims to provide an application-aware solution for communication infrastructure for FPGA-centric clusters. Specifically, our solution demonstrates application-awareness across multiple levels in the network stack, including low-level vii link protocols, router microarchitectures, routing algorithms, and applications. We start by investigating the low-level link protocol and the impact of its latency variance on performance. Our results demonstrate that, although some link jitter is always present, we can still assume near-synchronous communication on an FPGAcluster. This provides the necessary condition for statically-scheduled routing. We then propose two novel router microarchitectures for two different kinds of workloads: a wormhole Virtual Channel (VC)-based router for workloads with dynamic communication, and a statically-scheduled Virtual Output Queueing (VOQ)-based router for workloads with static communication. For the first (VC-based) router, we propose a framework that generates application-aware router configurations. Our results show that, by adding application-awareness into router configuration, the network performance of FPGA clusters can be substantially improved. For the second (VOQbased) router, we propose a novel offline collective routing algorithm. This shows a significant advantage over a state-of-the-art collective routing algorithm. We apply our communication infrastructure to a critical strong-scaling HPC kernel, the 3D FFT. The experimental results demonstrate that the performance of our design is faster than that on CPUs and GPUs by at least one order of magnitude (achieving strong scaling for the target applications). Surprisingly, the FPGA cluster performance is similar to that of an ASIC-cluster. We also implement the 3D FFT on another multi-FPGA platform: the Microsoft Catapult II cloud. Its performance is also comparable or superior to CPU and GPU HPC clusters. The second application we investigate is Molecular Dynamics Simulation (MD). We model MD on both FPGA clouds and clusters. We find ...

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“…There are published implementations for the Cell Broadband Engine processor, [25][26][27] for field-programmable gate arrays (FPGAs) [28][29][30][31] and custom chips [32][33][34][35] have also been built to accelerate MD simulations. An extensive overview about the use of FPGAs in MD is given by Khan et al 36…”

Section: Introductionmentioning

confidence: 99%

Classical molecular dynamics on graphics processing unit architectures

Jász¹,

Rák²,

Ladjánszki³

et al. 2019

WIREs Comput Mol Sci

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Molecular dynamics (MD) has experienced a significant growth in the recent decades. Simulating systems consisting of hundreds of thousands of atoms is a routine task of computational chemistry researchers nowadays. Thanks to the straightforwardly parallelizable structure of the algorithms, the most promising method to speed‐up MD calculations is exploiting the large‐scale processing power offered by the parallel hardware architecture of graphics processing units or GPUs. Programming GPUs is becoming easier with general‐purpose GPU computing frameworks and higher levels of abstraction. In the recent years, implementing MD simulations on graphics processors has gained a large interest, with multiple popular software packages including some form of GPU‐acceleration support. Different approaches have been developed regarding various aspects of the algorithms, with important differences in the specific solutions. Focusing on published works in the field of classical MD, we describe the chosen implementation methods and algorithmic techniques used for porting to GPU, as well as how recent advances of GPU architectures will provide even more optimization possibilities in the future. This article is characterized under: Software > Simulation Methods Computer and Information Science > Computer Algorithms and Programming Molecular and Statistical Mechanics > Molecular Dynamics and Monte‐Carlo Methods

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FPGA-Accelerated Molecular Dynamics

Cited by 14 publications

References 41 publications

On the Feasibility of FPGA Acceleration of Molecular Dynamics Simulations

On the Feasibility of FPGA Acceleration of Molecular Dynamics Simulations

High Performance Communication on Reconfigurable Clusters

Classical molecular dynamics on graphics processing unit architectures

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