FPGA Accelerated Low-Latency Market Data Feed Processing

Morris, Gareth W.; Thomas, David B.; Luk, Wayne

doi:10.1109/hoti.2009.17

Cited by 33 publications

(26 citation statements)

References 2 publications

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“…The depth is O(log(n)) and it needs n − 1 multiplexers and comparators. Note that the logic block of bitonic sort is inexpensive in terms of both time and logic resources because it only needs to sort five elements in the cache if price ≤ cache [5].price then 4: if cache.find(price) then 5: cache.at(price).total += quantity 6:…”

Section: E Discussionmentioning

confidence: 99%

“…cache [5] = (price, quantity) 8: sort(cache) 9: orderbook[addr] += quantity 10: (max, min) = orderbook.reduce(addr) 11: max.next = addr 12: addr.next = min 13: procedure HWCANCEL(price, quantity) 14: if price ≤ cache [5].price then 15: cache.at(price).total -= quantity …”

Section: E Discussionmentioning

confidence: 99%

“…If the price of the new order also belongs to the cache (the top 5 levels), the total quantity is accumulated if the price level of the new order is in the cache (line 3 to 5), or replace the last element of the cache because the price of the new order is smaller than that of cache [5] (line 7). A bitonic sort is then applied to keep the elements in the cache in order (line 8).…”

Section: A Hardware-friendly Addmentioning

confidence: 99%

“…It lists the number of shares being bid or offered at each price point [4]. By collecting the statistical information from order books, the OBU algorithm provides the traders with the changing status of the marketplace, called market data feeds, which enable the traders to reconstruct the marketplace, monitor market conditions, and perform algorithmic trading [5].…”

Section: Introductionmentioning

confidence: 99%

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Exploring the potential of reconfigurable platforms for order book update

Luk

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-The order book update (OBU) algorithm is widely used in financial exchanges for rebuilding order books. The number of messages produced has drastically increased over time. The software solutions become more and more difficult to scale with the growing message rate and meet the requirement of low latency. This paper explores the potential of reconfigurable platforms in revolutionizing the order book architecture, and proposes a novel order book update algorithm optimized for maximal throughput and minimal latency. Our approach has three main contributions. First, we derive a fixed tick data structure for the order book that is easier to be mapped to the hardware. Second, we design a customized cache storing the top five levels of the order book to further reduce the latency. Third, we propose a hardware-friendly order book update algorithm based on the data structures we proposed. In the experiment, our FPGA-based solution can process 1.2-1.5 million messages per second with the throughput of 10Gb/s and the latency of 132-288 nanoseconds, which is 90-157 times faster than a CPU-based solution, and 5.2-6.6 times faster than an existing FPGA-based solution.

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Section: E Discussionmentioning

confidence: 99%

Section: E Discussionmentioning

confidence: 99%

Section: A Hardware-friendly Addmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Exploring the potential of reconfigurable platforms for order book update

Luk

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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“…Morris [6] uses a Celoxica board to process financial messages, achieving a 3.5M messages per second throughput and hardware latency of 4μs. Their trading platform is one of the few including line arbitration, but no details of its performance are given.…”

Section: Background and Motivationmentioning

confidence: 99%

Network-Level FPGA Acceleration of Low Latency Market Data Feed Arbitration

Denholm

Inoue²,

Takenaka³

et al. 2015

IEICE Trans. Inf. & Syst.

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SUMMARYFinancial exchanges provide market data feeds to update their members about changes in the market. Feed messages are often used in time-critical automated trading applications, and two identical feeds (A and B feeds) are provided in order to reduce message loss. A key challenge is to support A/B line arbitration efficiently to compensate for missing packets, while offering flexibility for various operational modes such as prioritising for low latency or for high data reliability. This paper presents a reconfigurable acceleration approach for A/B arbitration operating at the network level, capable of supporting any messaging protocol. Two modes of operation are provided simultaneously: one prioritising low latency, and one prioritising high reliability with three dynamically configurable windowing methods. We also present a model for message feed processing latencies that is useful for evaluating scalability in future applications. We outline a new low latency, high throughput architecture and demonstrate a cycle-accurate testing framework to measure the actual latency of packets within the FPGA. We implement and compare the performance of the NAS-DAQ TotalView-ITCH, OPRA and ARCA market data feed protocols using a Xilinx Virtex-6 FPGA. For high reliability messages we achieve latencies of 42ns for TotalView-ITCH and 36.75ns for OPRA and ARCA. 6ns and 5.25ns are obtained for low latency messages. The most resource intensive protocol, TotalView-ITCH, is also implemented in a Xilinx Virtex-5 FPGA within a network interface card; it is used to validate our approach with real market data. We offer latencies 10 times lower than an FPGA-based commercial design and 4.1 times lower than the hardwareaccelerated IBM PowerEN processor, with throughputs more than double the required 10Gbps line rate.

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