2015
DOI: 10.1117/12.2079010
|View full text |Cite
|
Sign up to set email alerts
|

FPGA-accelerated adaptive optics wavefront control part II

Abstract: We present progressive work that is based on our recently developed rapid control prototyping system (RCP), designed for the implementation of high-performance adaptive optical control algorithms using a continuous deformable mirror (DM). The RCP system, presented in 2014, is resorting to a Xilinx Kintex-7 Field Programmable Gate Array (FPGA), placed on a self-developed PCIe card, and installed on a high-performance computer that runs a hard real-time Linux operating system. For this purpose, algorithms for th… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
5
0

Year Published

2016
2016
2024
2024

Publication Types

Select...
3
3

Relationship

2
4

Authors

Journals

citations
Cited by 6 publications
(6 citation statements)
references
References 6 publications
0
5
0
Order By: Relevance
“…In ref. [11], a Connected Components Labeling method (CCL) was used to detect the position of the spots, and the calculation of the centroid was carried out after the spot detection. The authors in ref.…”
Section: Introductionmentioning
confidence: 99%
“…In ref. [11], a Connected Components Labeling method (CCL) was used to detect the position of the spots, and the calculation of the centroid was carried out after the spot detection. The authors in ref.…”
Section: Introductionmentioning
confidence: 99%
“…Before the actual optical design can be developed, the required beam size at these individual elements needs to be determined. Since the AO control loop is based on the real-time FPGA based system developed in [1,2], the beam diameter at the wavefront sensor is already dictated. Furthermore, the tip/tilt mirror as applied in [2] is incorporated, which predetermines the respective beam size as well.…”
Section: A Beam Diameter Optimizationmentioning
confidence: 99%
“…Since the AO control loop is based on the real-time FPGA based system developed in [1,2], the beam diameter at the wavefront sensor is already dictated. Furthermore, the tip/tilt mirror as applied in [2] is incorporated, which predetermines the respective beam size as well. The AO system utilizes a unimorph deformable mirror manufactured at Fraunhofer IOF.…”
Section: A Beam Diameter Optimizationmentioning
confidence: 99%
“…The core of the board is Xilinx's Kintex7 series XC7K70T FPGA processor, which uses Xilinx's official PCIe hard core [2] to communicate with the driver. As a bridge between the application and the underlying hardware, the driver is mainly responsible for receiving the control commands from the application program and the image data from the FPGA, selecting the set image type by command, and using DMA to move the data transferred to the FPGA to the upper application according to the size of the image.…”
Section: The Hardware Structure Of Acquisition Cardmentioning
confidence: 99%