Four-quadrant CMOS current-mode multiplier independent of device parameters

Tanno, Koichi; Ishizuka, Okihiko; Tang, Zheng

doi:10.1109/82.842116

Cited by 82 publications

(39 citation statements)

References 6 publications

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“…The simulation results of the proposed four-quadrant current-mode multiplier are summarized and compared with the performance of the current-mode multiplier of [7] in Table 3. Also, the simulation results of the proposed four-quadrant voltage-mode multipliers are summarized and compared with the performance of the voltage-mode multiplier of [2] in Table 4.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Current-mode Proposed currentmultiplier mode multiplier presented in [7] Supply voltage supply voltages V DD and V SS are balanced (1.5 V and −1.5 V) respectively. Figure 5 shows the DC transfer characteristic of the four-quadrant current-mode multiplier of Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…This stems from its inherent advantages of wide bandwidth, high slow rate, low power consumption, and simple circuitry [4,5]. This is clearly obvious in the fourquadrant current-mode multipliers presented in [6,7] which based on current squarer cells.…”

Section: Introductionmentioning

confidence: 99%

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New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

Hashiesh

Mahmoud

Soliman

2005

Analog Integr Circ Sig Process

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In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ±60 µA, the bandwidth is 31 MHz, the input referred noise current is 46 pA/ √ Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ±1V from ±1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 µV/ √ Hz, and the maximum linearity error is 4.1%.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Simulation Resultsmentioning

confidence: 99%

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New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

Hashiesh

Mahmoud

Soliman

2005

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

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“…Following the early work of Gilbert [11], a variety of multipliers has been designed with different optimization objectives [12][13][14][15]. Multipliers have been built around various topologies using Bipolar, CMOS [12,13] and Bi-CMOS [14,15] based circuits.…”

Section: Introductionmentioning

confidence: 99%

“…Multipliers have been built around various topologies using Bipolar, CMOS [12,13] and Bi-CMOS [14,15] based circuits. The general idea behind these designs is to utilize electronic devices like BJT or MOS transistors to process the two input signals, followed by a cancellation of errors caused by non-linearity of the devices.…”

Section: Introductionmentioning

confidence: 99%

A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology

Makwana¹,

Sheth²

2012

VLSICS

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Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.

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Integrated CMOS impulse UWB receiver front‐end design

Miao

Nguyen

2009

Micro & Optical Tech Letters

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A single‐chip broadband CMOS receiver front‐end, integrating a low‐noise amplifier (LNA), a correlator, and a template pulse generator, was investigated in nonsinusoidal time‐domain environment for possible use as an impulse‐type ultra‐wideband (UWB) receiver front‐end. Particularly, the CMOS LNA and the multiplier making up the core component of the correlator were designed, fabricated, and tested to verify operation in the UWB range. Time‐domain results of the integrated CMOS receiver front‐end demonstrate its workability as a receiver for nonsinusoidal UWB applications. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2590–2595, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24682

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Four-quadrant CMOS current-mode multiplier independent of device parameters

Cited by 82 publications

References 6 publications

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology

Integrated CMOS impulse UWB receiver front‐end design

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