FOS: a low-power cache organization for multicores

Abstract

The cache hierarchy of current multicore processors typically consists of one or two levels of private caches per core and a large shared last level cache (LLC). This approach incurs area and energy wasting due to oversizing the private cache space, data replication through the inclusive cache levels, as well as the use of highly set-associative caches. In this paper, we claim that although this is the common adopted approach, it presents important design issues that can be addressed by a more energy efficient organization.This work proposes Flat On-chip Storage (FOS), a novel cache organization that, aimed at addressing energy and area on low-power processors, resolves the mentioned issues. For this purpose, FOS combines L2 and L3 cache levels into a single one, organized as a flat space, and composed of a pool of private small cache slices. These slices are initially powered off to save energy and they are powered on and assigned to cores provided that the system performance is expected to improve. To provide fast and uniform access from the private L1 caches to the FOS's cache slices, multiple architectural challenges are overcome, which entails the design of a custom Optical Network-on-Chip (ONoC).Experimental results show that FOS achieves significant energy savings on both static and dynamic energy over conventional cache organizations with the same storage capacity. FOS static energy savings are as much as 60% over an electrically-connected shared cache; these savings grow up to 75% compared to optically-connected baselines. Moreover, despite deactivating part of the cache space, FOS achieves similar performance values as those achieved by conventional approaches. Keywords Cache Hierarchy • Multicores • Energy efficiency 1 IntroductionMulticore processors have highly evolved during the last decade. Early multicores consisted of only two cores, and progressively the core count increased with technology advances. Multicores, especially tiled multicores, are designed as a set of cores, each one including