Formation of regular step arrays on Si(111)7×7

Lin, Ja‐Chen; Petrovykh, Dmitri Y.; Viernow, J.; Men, F. K.; Seo, Dongjea; Himpsel, F. J.

doi:10.1063/1.368077

Cited by 127 publications

(78 citation statements)

References 32 publications

(42 reference statements)

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“…[5][6][7] Steps on Si͑111͒ vicinal surfaces have been decorated by metals, 3,8 semiconductors, 4,9 and organic molecules. 10 The challenge is to improve the homogeneity of the nanowire array and the crystallinity and the aspect ratio of the wires.…”

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confidence: 99%

“…[2][3][4] A suitable template is the vicinal surface of a Si͑111͒ single crystal, since the structure of the step train on this surface can be controlled to a large extent. [5][6][7] Steps on Si͑111͒ vicinal surfaces have been decorated by metals, 3,8 semiconductors, 4,9 and organic molecules. 10 The challenge is to improve the homogeneity of the nanowire array and the crystallinity and the aspect ratio of the wires.…”

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confidence: 99%

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Optimized Ge nanowire arrays on Si by modified surfactant mediated epitaxy

Romanyuk¹,

Mysliveček

Cherepanov³

et al. 2007

Phys. Rev. B

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We demonstrate the formation of Ge nanowire arrays on highly ordered kink-free Si stepped surfaces. The nanowires are grown using Bi surfactant mediated epitaxy. The nanowires are single crystalline and feature minimal kink densities, allowing them to span lengths larger than 1 m at a width of Ϸ4 nm. To achieve desired growth conditions for the formation of such nanowire arrays, we explore a full parameter space of surfactant mediated epitaxy. We show that controlling the surfactant coverage in the surface and/or at step edges modifies the growth properties of surface steps in a decisive way. DOI: 10.1103/PhysRevB.75.241309 PACS number͑s͒: 61.46.Ϫw, 81.16.Dn, 81.15.Hi, 68.37.Ef In order to fabricate ever-smaller nanoscale device structures, there is an enormous interest in finding ways to build devices from the bottom up rather than fabricate from the top down. Using the bottom-up approach, the size of the structures is not limited by lithography; however, the uniformity and the ability to position the nanostructures are still challenges. Specifically, nanowires are desirable as nanoscale interconnects.1 One of the concepts followed in the bottom-up formation of nanowire arrays is to create a highly ordered atomic-step template on a vicinal single-crystal surface and to form the wires along the step edges, decorating the step edges with a selected material.2-4 A suitable template is the vicinal surface of a Si͑111͒ single crystal, since the structure of the step train on this surface can be controlled to a large extent. [5][6][7] Steps on Si͑111͒ vicinal surfaces have been decorated by metals, 3,8 semiconductors, 4,9 and organic molecules. 10 The challenge is to improve the homogeneity of the nanowire array and the crystallinity and the aspect ratio of the wires.Recently, we made two contributions to these efforts. First, we developed a method to grow high-aspect-ratio single-crystalline Ge nanowires at Si͑111͒ step edges. 4 We used surfactant mediated epitaxy 9 where the surfactant ͑Bi͒ always floats at the growth front, covering both the Si surface and the Ge nanowires. The surfactant prevented mutual Ge-Si intermixing and mediated a chemical contrast between Si and Ge, allowing observation of the lateral Ge-Si nanostructures in a scanning tunneling microscope ͑STM͒. Second, we developed a method to obtain an improved ordering of the step train on the Si͑111͒-7 ϫ 7 surface by precise mechanical polishing of Si wafers and subsequent controlled annealing in vacuum. 7 We obtain surface steps that are kinkfree, atomically straight, and largely equidistant at scales of 1 ϫ 1 m 2 ͓Figs. 1͑a͒ and 1͑b͔͒. 7In this work we show how it is possible to create a highly ordered array of Ge nanowires on the Bi-covered Si͑111͒ surface ͓Figs. 1͑c͒-1͑f͔͒. A straightforward combination of the above two techniques 4,7 does not yield the desired result. The important point is to conserve the long-range order of the initial Si template, which is usually lost during the nanowire preparation process using standard surfactant media...

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mentioning

confidence: 99%

Optimized Ge nanowire arrays on Si by modified surfactant mediated epitaxy

Romanyuk¹,

Mysliveček

Cherepanov³

et al. 2007

Phys. Rev. B

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“…STM measurements were performed between T = 5.2 − 6.5 K where indicated. Vicinal Si(111) samples (1.1 • miscut toward [112]) utilized were n-doped (Sb) with a resistivity of 0.022 − 0.06 Ω-cm 26 . Pb was deposited on Si(111) − 7 × 7 from a thermal evaporator with typical growth rates of 0.5 ML per minute at room temperature, resulting in flat-top mesas 19,27,28 .…”

Section: Experimental and Computational Methodsmentioning

confidence: 99%

Adsorbate-induced restructuring of Pb mesas grown on vicinal Si(111) in the quantum regime

et al. 2009

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Using scanning tunneling microscopy and spectroscopy, we demonstrate that the adsorption of a minute amount of Cs on a Pb mesa grown in the quantum regime can induce dramatic morphological changes of the mesa, characterized by the appearance of populous monatomic-layer-high Pb nanoislands on top of the mesa. The edges of the Pb nano-islands are decorated with Cs adatoms, and the nano-islands preferentially nucleate and grow on the quantum mechanically unstable regions of the mesa. Furthermore, first-principles calculations within density functional theory show that the Pb atoms forming these nano-islands were expelled by the adsorbed Cs atoms via a kinetically accessible place exchange process when the Cs atoms alloyed into the top layer of the Pb mesa.

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“…16 Himpsel and co-workers have experimentally demonstrated that vicinal Si͑111͒ surfaces can serve as templates for self-assembly of one-dimensional ͑1D͒ nanostructures, 17,18 because a regular array of straight steps can be obtained on these surfaces. [19][20][21] Improving their method of the straight-step preparation by substrate annealing with step-parallel direct current ͑dc͒, we have found that the "kink-up" direction ͑ascending kinks of the steps͒ of the dc is effective to obtain atomically straight step edges ͑on the order of 1 m in length͒ probably due to electromigration of the surface atoms. 22 We have studied the growth behavior of Si ͑Ref.…”

Section: Introductionmentioning

confidence: 99%

Self-assembly of periodic nanoclusters of Si and Ge along atomically straight steps of a vicinal Si(111)

Sekiguchi

Yoshida

Shiren

et al. 2007

Journal of Applied Physics

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The very initial stage of the molecular beam epitaxy of Si and Ge on Si͑111͒ −7ϫ 7 substrates with atomically straight steps has been studied by scanning tunneling microscopy and spectroscopy. The atomically straight steps have been prepared on a miscut Si͑111͒ substrate by annealing at 830°C with kink-up direct current. The length of the steps can be maximized by selecting a proper annealing time. The steps have a well-defined U͑2, 0͒ step-edge structure. The growth of both Si and Ge at temperatures between 250 and 400°C starts with formation of a single-adatom-row nanowire ͑0.67 nm in width͒ along the lower edge of each U͑2, 0͒ step. Subsequent growth of Si and Ge at temperatures between 250 and 300°C results in formation of one-dimensional arrays of nanoclusters ͑less than 2.0 nm in width͒ in the unfaulted halves of the 7 ϫ 7 structure along the upper step edges. Scanning tunneling spectroscopy reveals localized electronic states of the nanoclusters. Differences between the growth of Si and Ge nanoclusters are discussed.

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Formation of regular step arrays on Si(111)7×7

Cited by 127 publications

References 32 publications

Optimized Ge nanowire arrays on Si by modified surfactant mediated epitaxy

Optimized Ge nanowire arrays on Si by modified surfactant mediated epitaxy

Adsorbate-induced restructuring of Pb mesas grown on vicinal Si(111) in the quantum regime

Self-assembly of periodic nanoclusters of Si and Ge along atomically straight steps of a vicinal Si(111)

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