Formation of basal plane dislocations by stress near epilayer/substrate interface of large-diameter SiC wafers with thick epitaxial layers

Abstract

For large-diameter (150 mm) SiC epitaxial wafers with thick n− epilayers, stress analysis based on the finite element method and defect characterization near the epi/sub interface by synchrotron x-ray topography were performed. Observations on epitaxial wafers with epilayer thicknesses of 10, 20, 50, and 100 μm revealed that basal plane dislocation (BPD) half-loops were formed near triangular defects or from the edge of the wafer at an epilayer thickness of 50 μm and above. Two types of BPD half-loops with different edge components were observed: one with an extra half-plane above the core and present on the substrate side, and the other with a Burgers vector of opposite sign and present in the epilayer and at the epi/sub interface, forming an interfacial dislocation. The signs of these BPDs are consistent with those predicted from the calculation results, which mitigate compressive and tensile stresses in the epilayer and the substrate, respectively. It is considered that a thicker epilayer increases tensile stress in the substrate, which induces the formation of the BPD with an extra half-plane above the core on the substrate side. The distribution of the BPD half-loop width was also analyzed and compared with the calculated shear stress distribution caused by the radial temperature gradient. Calculations considering the local stress near the triangular defect revealed that the tensile stress near the epi/sub interface locally increases, exceeding the critical stress to form BPD, with an extra half-plane above the core for wafers with an epilayer thickness above 50 μm.