Formation of a defect-free junction layer by controlling defects due to As/sup +/ implantation

Onishi, S.; Ayukawa, A.; Sakiyama, K.

doi:10.1109/relphy.1991.146024

Cited by 7 publications

(1 citation statement)

References 6 publications

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“…I and 2). Gate edge line defects, originating in S/D regions and protruding under sidewall oxide, resemble defects reported to be responsible for electrical leakage and single bit failures (1)(2)(3)(4)(5). Gate edge defects are approximately 3 to 5• more numerous in B-implanted regions than in As-implanted regions.…”

Section: Resultsmentioning

confidence: 87%

Effect of Device Processing Conditions on Extended Dislocations and Defects in Ti‐Salicided Source/Drain Regions of Silicon Integrated Circuits

Guldi

1993

J. Electrochem. Soc.

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The propagation of incipient n+ and p+ source/drain (S/D) implant damage into extended dislocations at gate and field edges was studied for a variety of different processing conditions used to fabricate typical Ti‐salicided complimentory metal oxide semiconductor transistors. Gate edge dislocations were observed predominantly in n‐wells, while field edge defects occurred in both n and p‐wells. Both gate edge and field edge dislocations were found to be strongly affected by stresses from field oxide edges and overlying dielectric spacer layers. The use of a low‐stress polysilicon‐to‐metal dielectric is effective in reducing the density of extended dislocations in both n‐ and p‐wells. Moderation of field oxide edge stress, either by reducing the field oxide thickness or by tapering the field to active area transition region, is also effective in reducing dislocation density in the n‐well.

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