Formal verification of VHDL descriptions in the Prevail environment

Abstract. We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosis-oriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size.

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“…Our prototype diagnosis system is now a part of the PREVAIL TM environment [19] and is being tested on industrial applications.…”

Section: Resultsmentioning

confidence: 99%

A method for automatic design error location and correction in combinational logic circuits

Wahba

Borrione

1996

J Electron Test

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“…· Peter T. Breuer et al Temporal logics have typically been used in model checking approaches to the verification of medium-sized hardware circuits, but their application to VHDL has had to wait upon complete and tractable formal semantics for the language. And although finite-state machine approaches to the nondelay parts of VHDL codes have been pursued for some while (e.g., Borrione et al [1992]), the first effort at a more complete operational semantics [van Tassel 1990; is still recent.…”

Section: Introductionmentioning

confidence: 99%

A refinement calculus for the synthesis of verified hardware descriptions in VHDL

Breuer

Delgado

Marín

et al. 1997

ACM Trans. Program. Lang. Syst.

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A formal refinement calculus targeted at system-level descriptions in the IEEE standard hardware description language VHDL is described here. Refinement can be used to develop hardware description code that is ''correct by construction." The calculus is closely related to a Hoare-style programming logic for VHDL and real-time systems in general. That logic and a semantics for a core subset of VHDL are described. The programming logic and the associated refinement calculus are shown to be complete. This means that if there is a code that can be shown to implement a given specification, then it will be derivable from the specification via the calculus.

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“…This is the approach we took to develop the PREVAIL prototype, a multi-proof tool environment taking VHDL descriptions as inputs [7]. In the current status of PREVAIL, we can process a syntactic subset of VHDL for zero-delay combinational circuits and single clock synchronized sequential circuits, and require the adoption of description styles for synchronous sequential circuits; functional semantics are associated with the subset and styles.…”

Section: Introductionmentioning

confidence: 99%