Formal Verification of the VAMP Floating Point Unit

Berg, Christoph; Jacobi, Christian

doi:10.1007/3-540-44798-9_26

Cited by 18 publications

(17 citation statements)

References 15 publications

(24 reference statements)

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“…This library was then used in the verification of IEEE-compliant floating-point arithmetic algorithms [5] and hardware units [6]. Berg et al [3] have formally verified a theory of IEEE rounding presented in [32] using the theorem prover PVS. They have used a formal definition of rounding based on Miner's formalization of the standard [29].…”

Section: Related Workmentioning

confidence: 99%

Formalization of Fixed-Point Arithmetic in HOL

Akbarpour

Tahar

Dekdouk

2005

Form Method Syst Des

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Abstract. This paper addresses the formalization in higher-order logic of fixed-point arithmetic. We encoded the fixed-point number system and specified the different quantization modes in fixed-point arithmetic such as the directed and even quantization modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the quantized result after carrying out basic arithmetic operations, such as addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used to enable the verification of the transition from floating-point to fixed-point algorithmic level in the signal processing design flow.

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Section: Related Workmentioning

confidence: 99%

Formalization of Fixed-Point Arithmetic in HOL

Akbarpour

Tahar

Dekdouk

2005

Form Method Syst Des

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“…The work done by Russinoff described in [14] and [15] on the AMD K7 and Athlon FP units and the VAMP FP unit described in [3] make use of theorem proving. The Intel FP unit verification by John O'Leary mentioned in [11] and by Aagaard and Seger in [1] makes use of a mixture of theorem proving and model checking.…”

Section: Introductionmentioning

confidence: 99%

Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification

Kikkeri

Seidel

2006

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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The formal verification of optimized arithmetic circuits imposes several challenges. Performance-optimized IEEE floating-point implementations can be particularly hard verification cases for their size and their irregularities, for the redundancy that is often used in the representations of intermediate values, and by the complex non-standard logic optimizations that are incorporated in the designs. We formally verify the highly optimized Even-Seidel rounding algorithm for IEEE floating-point multiplication and IEEE floating-point addition which incorporates the use of rounding injections. Our verification efforts are based on the PVS theorem-prover. We structure the whole verification process in a hierarchical fashion where existing specifications and properties are re-used to ease the overall effort. We show the benefits of our hierarchical approach by verifying two variants of the algorithm for performance optimized IEEE floatingpoint multiplication and IEEE floating-point addition.

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“…As the verified unit is part of an industrial product not all details have been published. Based on the constructions and on the paper and pencil proofs in [18] a fully IEEE compatible FPU has been verified [1,11] (using mostly but not exclusively theorem proving). iv) Caches.…”

Section: Introductionmentioning

confidence: 99%

“…Except for the work on floating point units, the cache coherence protocol in [6], and the FM9001 processor [2], none of the papers quoted above states that the verified design actually has been implemented. All results cited above except [1,2,6,11] use several simplifications and abstractions:…”

Section: Introductionmentioning

confidence: 99%

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Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP

Beyer

Jacobi²,

Kröning

et al. 2003

Lecture Notes in Computer Science

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Abstract. In the VAMP (verified architecture microprocessor) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA.

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Formal Verification of the VAMP Floating Point Unit

Cited by 18 publications

References 15 publications

Formalization of Fixed-Point Arithmetic in HOL

Formalization of Fixed-Point Arithmetic in HOL

Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification

Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP

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