Formal Verification of Hardware Synthesis

Abstract

We report on the implementation of a certified compiler for a high-level hardware description language (HDL) called Fe-Si (FEatherweight SynthesIs). Fe-Si is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. Fe-Si is defined as a dependently typed deep embedding in Coq. The target language of the compiler corresponds to a synthesisable subset of Verilog or VHDL. A key aspect of our approach is that input programs to the compiler can be defined and proved correct inside Coq. Then, we use extraction and a Verilog back-end (written in OCaml) to get a certified version of a hardware design.

Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq

“…The whole work has been carried out in the theorem prover Coq. This paper and our previous work can be further extended in future to automatically generate HDL codes for hardware design as discussed in [11].…”

VeriCoq: A Verilog-to-Coq converter for proof-carrying hardware automation

“…Therefore, in order to be applicable and leverage the rich collection of hardware IPs developed in HDLs such as Verilog and VHDL, PCHIP defines conversion rules from HDLs to a Coq representation. Consequently, PCHIP does not intervene in the current hardware IP design and test methodology, as is the case when introducing a new formal HDL [12]. Rather, it adds extra steps in parallel to the current design methodology, namely conversion to Coq, stating security properties as theorems in Coq, constructing proofs for such theorems based on the hardware design and delivering those proofs along with the HDL code to the IP consumer.…”

Compiler verification for fun and profit

“…For example, functional languages and object-oriented languages raise the issue of jointly verifying the compiler and the run-time system (memory management, exception handling, etc) that the generated code depends on. At the other end of the expressiveness spectrum, synchronous languages and hardware description languages also raise interesting verified generation issues, as exemplified by Pnueli's seminal work on translation validation for Signal [6] and Braibant and Chlipala's recent work on verified hardware synthesis [7].…”