Formal verification of automatic circuit transformations for fault-tolerance

Burlyaev, Dmitry; Fradet, Pascal

doi:10.1109/fmcad.2015.7542251

Cited by 1 publication

(1 citation statement)

References 17 publications

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“…error-correction code (ECC) based mechanisms against single-bit errors in memory elements [68]. [34] proposes a general approach to verify gate-level design transformations for reliability against single-event transients by soft errors that combines formal reasoning on execution traces. [35] and [36] focus on the RAS (reliability, availability and serviceability) group of extrafunctional aspects outlined by IBM for complex processor designs where embedded error protection mechanisms and designs intrinsic immunity (due to various masking) to errors is evaluated by fault injection.…”

Section: B Reliability Aspectsmentioning

confidence: 99%

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Jenihhin

Lai

Ghasempouri

et al. 2018

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Trends in advanced electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) assume devices immersed in physical environments, significantly constrained in resources and expected to provide levels of security, privacy, reliability, performance and low power features. In recent years, numerous extra-functional aspects of electronic systems were brought to the front and imply verification of hardware design models in multidimensional space along with the functional concerns of the target system. However, different from the software domain such a holistic approach remains underdeveloped. The contributions of this paper are a taxonomy for multidimensional hardware verification aspects, a state-of-the-art survey of related research works and trends towards the multidimensional verification concept. The concept is motivated by an example for the functional and power verification dimensions.

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