Formal Verification of an Avionics Application using Abstraction and Symbolic Model Checking

Bienmüller, Tom; Brockmeyer, Udo; Damm, Werner; Döhmen, Gert; Eßmann, Claus; Holberg, Hans-Jürgen; Hungar, Hardi; Josko, Bernhard; Schlör, Rainer; Wittich, Gunnar; Wittke, Hartmut; Clements, G. B.; Rowlands, J. A.; Sefton, Eric

doi:10.1007/978-1-4471-0823-8_10

Cited by 11 publications

(17 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…par of subs of V represents the construction for particular node's subcharts. Processes representing subcharts in different substates are synchronised, together with the TopMach() 3 . Actions progress by inner machines are controlled by events proceed, and all actions within this chart and not controlled outside is renamed to progress.…”

Section: Hierarchical Structuringmentioning

confidence: 99%

See 1 more Smart Citation

Verifying Statemate Statecharts Using CSP and FDR

Roscoe

2006

Formal Methods and Software Engineering

View full text Add to dashboard Cite

show abstract

Section: Hierarchical Structuringmentioning

confidence: 99%

“…Clarke and his colleagues have developed the SMV tool for checking finite state systems against specifications in the temporal logic CTL [4][5][6]. Work by Bienmuller, Damm and their colleagues has built up the STVE to model and verify some industrial applications [2,3,7,11].…”

Section: Introductionmentioning

confidence: 99%

Verifying Statemate Statecharts Using CSP and FDR

Roscoe

2006

Formal Methods and Software Engineering

View full text Add to dashboard Cite

show abstract

“…If a channel is used, the input command Q?Ev is used. 8. In order to identify the candidate transitions for firing, a boolean variable Cand_i corresponding to the transition t_i in the EHA is used.…”

Section: Translating Uml Statecharts To Promela/spin [Latella Et Al mentioning

confidence: 99%

“…This work is reported in a series of papers by Werner Damm and his coworkers at OFFIS, University of Oldenburg [7,8,10], which describe the transition from a prototype verification system for STATEMATE to a commercial product from i-Logix. The salient features of the STATEMATE Verification Environment are listed below.…”

Section: The Statemate Verification Environment [Damm Et Al 2000]mentioning

confidence: 99%

Whither neurosurgical teaching?

Ramesh¹

2006

Neurol India

View full text Add to dashboard Cite

We survey existing approaches to the formal verification of statecharts using model checking. Although the semantics and subset of statecharts used in each approach varies considerably, along with the model checkers and their specification languages, most approaches rely on translating the hierarchical structure into the flat representation of the input language of the model checker. This makes model checking difficult to scale to industrial models, as the state space grows exponentially with flattening. We look at current approaches to model checking hierarchical structures and find that their semantics is significantly different from statecharts. We propose to address the problem of state space explosion using a combination of techniques, which are proposed as directions for further research.

show abstract

“…This paper reports on a successful technology transfer, taking a prototype verification system for Statemate [2,5] to a version available as commercial product offering. It is only through the significant improvements reported in this paper that key companies are now taking up this technology in an industrial setting.…”

Section: Introductionmentioning

confidence: 99%

The Statemate Verification Environment

Bienmüller¹,

Damm

Wittke

2000

Computer Aided Verification

Self Cite

View full text Add to dashboard Cite

The Statemate Verification Environment supports requirement analysis and specification development of embedded controllers as part of the Statemate product offering of I-Logix, Inc. This paper discusses key enhancements of the prototype tool reported in [2,5] in order to enable full scale industrial usage of the tool-set. It thus reports on a successfully completed technology transfer from a prototype tool-set to a commercial offering. The discussed enhancements are substantiated with performance results all taken from real industrial applications of leading companies in automotive and avionics.

show abstract

Formal Verification of an Avionics Application using Abstraction and Symbolic Model Checking

Cited by 11 publications

References 2 publications

Verifying Statemate Statecharts Using CSP and FDR

Verifying Statemate Statecharts Using CSP and FDR

Whither neurosurgical teaching?

The Statemate Verification Environment

Contact Info

Product

Resources

About