Formal verification made easy

Abstract

Formal verification (FV) is considered by manyto be complicated and to require considerable mathematical knowledge for successful application. We have developed a methodology in which we have added formal verification to the verification process without requiring any knowledge of formal verification languages. We use only finite-state machine notation, which is familiar and intuitive to designers. Another problem associated with formal verification is state-space explosion. If that occurs, no result is returned; our method switches to random simulation after one hour without results, and no effort is lost. We have compared FV against random simulation with respect to development time, and our results indicate that FV is at least as fast as random simulation. FV is superior in terms of verification quality, however, because it is exhaustive.

Branching vs. Linear Time: Final Showdown

“…The linear framework is simply more natural for verification engineers, who tend to think linearly, e.g., timing diagrams [37] and message-sequence charts [64], rather than "branchingly". IBM's experience with the RuleBase system has been that "nontrivial CTL equations are hard to understand and prone to error" [90] and "CTL is difficult to use for most users and requires a new way of thinking about hardware" [7]. Indeed, IBM has been trying to "linearize" CTL in their RuleBase system [7].…”

Guest editors’ introduction: Model checking in a nutshell

“…Model checking is a widely accepted technique for the design phases that deal with circuits at the register transfer level and the gate level. Industrial experiments have provided evidence that model checking is no worse than random simulation in terms of time spent and that it is clearly superior in terms of coverage [25].…”

EDA in IBM: past, present, and future

“…Many RuleBase innovations involve methods that address the model size problem of BDD-based model checking. As a result, RuleBase was successfully applied to designs [27] like bus bridges, cache controllers, bus interface units, and functional units of microprocessors, and pushed this new technology into the mainstream verification process.…”