Formal Verification based on Boolean Expression Diagrams

Computer Aided Verification

2001

The property of Positive Equality [2] dramatically speeds up validity checking of formulas in the logic of Equality with Uninterpreted Functions and Memories (EUFM) [4]. The logic expresses correctness of high-level microprocessors. We present EVC (Equality Validity Checker)-a tool that exploits Positive Equality and other optimizations when translating a formula in EUFM to a propositional formula, which can then be evaluated by any Boolean satisfiability (SAT) procedure. EVC has been used for the automatic formal verification of pipelined, superscalar, and VLIW microprocessors. 2 Hardware Description Language In order to be verified with EVC, a high-level implementation processor and its specification must be defined in our Hardware Description Language (HDL).

Section: Summary Of Resultsmentioning

confidence: 99%

“…The propositional formula can be output in a variety of formats, including CNF and ISCAS, allowing the use of many SAT procedures for evaluating it. BDD [6] and BED [23] packages are integrated in EVC.…”

Section: Tool Flowmentioning

confidence: 99%

EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations

Computer Aided Verification

2001

Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction

Proceedings of the 37th Conference on Design Automation - DAC '00

2000

We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors to be applicable to designs where the functional units and memories have multicycle and possibly arbitrary latency. We also show ways to incorporate exceptions and branch prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted Functions [4][5]. We study the modeling of the above features in different versions of dualissue superscalar processors.

Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW

Proceedings of the 38th Conference on Design Automation - DAC '01

2001

We compare SAT-checkers and decision diagrams on the evaluation of Boolean formulas produced in the formal verification of both correct and buggy versions of superscalar and VLIW microprocessors. We identify one SAT-checker that significantly outperforms the rest. We evaluate ways to enhance its performance by variations in the generation of the Boolean correctness formulas. We reassess optimizations previously used to speed up the formal verification and probe future challenges.15.1 15.1