Formal Timing Analysis of Full Duplex Switched Based Ethernet Network Architectures

Rox, Jonas; Ernst, Rolf

doi:10.4271/2010-01-0455

Cited by 22 publications

(21 citation statements)

References 9 publications

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“…A similar approach has been shown for regular Ethernet in Rox and Ernst (2010) and for networks-on-chip in e.g. Shi and Burns (2008) and Diemer et al (2011).…”

Section: Background and Related Workmentioning

confidence: 98%

Modeling of Ethernet AVB Networks for Worst-Case Timing Analysis

Diemer

Rox

Ernst

2012

IFAC Proceedings Volumes

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“…A similar approach has been shown for regular Ethernet in Rox and Ernst (2010) and for networks-on-chip in e.g. Shi and Burns (2008) and Diemer et al (2011).…”

Section: Background and Related Workmentioning

confidence: 98%

Modeling of Ethernet AVB Networks for Worst-Case Timing Analysis

Diemer

Rox

Ernst

2012

IFAC Proceedings Volumes

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“…We assume that frames in the Ethernet network are scheduled according to IEEE 802.1Q, i.e. in a static-priority non-preemptive way (Rox and Ernst 2010;Thiele et al 2014). A detailed discussion of the modeling and timing analysis of the gateways is given in the following section.…”

Section: Modeling Automotive Networkmentioning

confidence: 99%

“…Revsbech et al (2011). Formal timing analysis using CPA for strict-priority Ethernet was presented in Rox and Ernst (2010). In Bauer et al (2010) the trajectory approach was applied to analyze Avionics Full Duplex Switched Ethernet (AFDX).…”

Section: Related Workmentioning

confidence: 99%

Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks

et al. 2015

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Due to increased bandwidth and scalability demands, Ethernet technology is finding its way into recent in-vehicle networks. Tomorrow's heterogeneous networks will feature legacy buses [e.g. controller area network (CAN) or FlexRay] as well as high-speed Ethernet devices, connected by switches and gateways. As Ethernet offers significantly larger frame sizes than CAN, the efficient transmission of CAN data over an Ethernet backbone depends heavily on the way this data is multiplexed into Ethernet frames. This article focuses on the timing impact introduced by various CAN/Ethernet multiplexing strategies at the gateways. We present a formal analysis method to derive upper bounds on end-to-end latencies for complex multiplexing strategies, which is key for the design of safety-critical real-time systems. We capture complex interdomain signal paths spanning multiple buses, gateways, and switches and show the applicability in a realistic automotive setup.

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“…In [21] periodic flows with known offsets in source ESs are considered to eliminate some pessimistic scenarios, which lead to a reduction of delay upper bounds. In [22], the eventstream model formulated with a staircase model is applied to obtain upper bounds of traffic. Another solution to determine the delay upper bounds is the trajectory approach, which considers the worst-case scenario experienced by a frame along its path [23]- [29].…”

Section: Related Workmentioning

confidence: 99%