Formal semantics for PSL modeling layer and application to the verification of transactional models

Ferro,; Pierre,

doi:10.1109/date.2010.5456991

Cited by 14 publications

(3 citation statements)

References 14 publications

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“…Traulsen et al [17] translate SystemC models into Promela models that enables them to use a model checker to verify LTL properties. Ferro and Pierre [18, 19] describe a framework, for verifying temporal SystemC‐TLM properties using PSL properties. They use the observer pattern technique for evaluating assertions, each time a variable of an assertion has been modified.…”

Section: Related Workmentioning

confidence: 99%

System‐level assertions: approach for electronic system‐level verification

Sohofi¹,

Navabi²

2015

IET Computers & Digital Techniques

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As design of digital systems become more complex and more transistors are incorporated into a single chip, design and verification methodologies moves into higher levels. Now that design at the register transfer level (RTL) has reached its maturity, the focus is shifting to electronic system level (ESL) design tools, languages and methodologies. At the centre of this and perhaps the most challenging are verification methods and tools to use for verifying designs at the ESL. This study presents a new concept of system-level assertions for ESL verification. It also demonstrates an environment for functionally verifying system-level designs using these system-level assertions. The proposed environment adapts existing EDA simulation tools, which are mainly used for RTL design and verification, and utilises them for system-level verification. In this environment, designs are modelled in SystemC-transaction level modelling 2.0, and assertions are written in SystemVerilog. Design and verification parts are connected together using SystemVerilog Direct Programming Interface mechanism, and designs that are described in SystemC are verified against system-level assertions in the course of SystemVerilog simulation.

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Section: Related Workmentioning

confidence: 99%

System‐level assertions: approach for electronic system‐level verification

Sohofi¹,

Navabi²

2015

IET Computers & Digital Techniques

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“…Ferro and Pierre [15,16] describe a prototype implementation for verifying temporal SystemC properties. Only the simple subset of the Foundation Language class of PSL is supported, and application of the methodology is restricted to TLM models.…”

Section: Related Workmentioning

confidence: 99%

Automatic aspectization of systemC

Tabakov

Vardi

2012

Proceedings of the 2012 Workshop on Modularity in Systems Software

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A successful monitoring framework for SystemC requires access to internal variables of modules and channels, and the ability to trace the execution of threads and methods. We propose a framework for automatically instrumenting user code and exposing its state and syntax via automatically generated Aspect-Oriented Programming code and direct instrumentation. This allows monitoring the execution with a finegrained temporal resolution. Our tool, CHIMP, allows the users to declare specification primitives referring to the values of internal variables, the values of parameters passed to function calls, and function return values. Tracing execution of processes is enabled by allowing statements' execution or function calls to be used as atomic propositions. The correct behavior of the model can then be specified by forming temporal formulas and clock expressions using these primitives, without requiring manual instrumentation of the user code.

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“…For instance, these include design methodologies [4], algorithms for design space exploration [5], [6] and verification approaches [7], [8], [9], [10], [11], [12], [13]. However, the existing debugging solutions for SystemC TLM have serious limitations (for a detailed discussion we refer to the related work section).…”

Section: Introductionmentioning

confidence: 99%

Automatic Fault Localization for SystemC TLM Designs

Große

Drechsler

2010

2010 11th International Workshop on Microprocessor Test and Verification

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Abstract-To meet today's time-to-market demands catching bugs as early as possible during the design of a system is absolutely essential. In Electronic System Level (ESL) design where SystemC has become the de-facto standard due to Transaction Level Modeling (TLM), many approaches for verification have been developed. They determine an error trace which demonstrates the difference between the required and the actual behavior of the system. However, the subsequent debugging process is very time-consuming, in particular due to TLMrelated faults caused by complex process synchronization and concurrency.In this paper, we present an automatic fault localization approach for SystemC TLM designs. The approach determines components that can be changed such that the intended behavior of the design is obtained removing the contradiction given by the error trace. Techniques based on Bounded Model Checking (BMC) are used to find the components. We demonstrate the quality of our approach by experimental results.

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Formal semantics for PSL modeling layer and application to the verification of transactional models

Cited by 14 publications

References 14 publications

System‐level assertions: approach for electronic system‐level verification

System‐level assertions: approach for electronic system‐level verification

Automatic aspectization of systemC

Automatic Fault Localization for SystemC TLM Designs

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