Formal online methods for voltage/frequency control in multiple clock domain microprocessors

Abstract

Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain independently.Most existing DVFS approaches are profile-based offline schemes which are mainly suitable for applications whose execution characteristics are constrained and repeatable. While some work has been published about online DVFS schemes, the prior approaches are typically heuristic-based. In this paper, we present an effective online DVFS scheme for an MCD processor which takes a formal analytic approach, is driven by dynamic workloads, and is suitable for all applications.In our approach, we model an MCD processor as a queue-domain network and the online DVFS as a feedback control problem with issue queue occupancies as feedback signals. A dynamic stochastic queuing model is first proposed and linearized through an accurate linearization technique. A controller is then designed and verified by stability analysis. Finally we evaluate our DVFS scheme through a cycle-accurate simulation with a broad set of applications selected from MediaBench and SPEC2000 benchmark suites. Compared to the best-known prior approach, which is heuristicbased, the proposed online DVFS scheme is substantially more effective due to its automatic regulation ability. For example, we have achieved a 2-3 fold increase in efficiency in terms of energy-delay product improvement. In addition, our control theoretic technique is more resilient, requires less tuning effort, and has better scalability as compared to prior online DVFS schemes.We believe that the techniques and methodology described in this paper can be generalized for energy control in processors other than MCD, such as tiled stream processors.

Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors

“…However, similar to the observation in [23], we notice that the position of q ref specifies the actual tradeoff between performance degradation and energy saving. We can increase q ref to make the DVFS controller more aggressive in saving energy, or decrease q ref to preserve performance more.…”

“…So this scheme is useful for processors with limited hardware budgets. Third, for a group of applications with fast workload variations, the current scheme outperforms existing online DVFS schemes for MCD significantly due to its self-tuning reactive nature (on average, 18% better than [23], and nearly 3 fold better than [19]). So this scheme is also useful and suitable to processors where the type of application behavior (i.e.…”

“…The energy cost part for the DVFS switching comes from the voltage regulator (VR) [4]. Since the capacitor in VR is relatively small (most VRs are dual-phased so there are two output capacitors), the switching energy cost is small and is ignored in most DVFS studies [11,14,19,23]. The time cost is the main concern in DVFS switching.…”

“…Specifically, during the time interval, certain system metrics or statistics are monitored, such as IPC [8] or average issue queue occupancy [19,23]. At the end of the interval, the statistics from the current and past intervals are used to compute a new voltage/frequency setting for future intervals.…”

Having your cake and eating it too: Energy savings without performance loss through resource sharing driven power management

“…The objective in either case is to reduce the supply voltage and operating frequency when the workload demand is low so that energy can be saved without significant performance degradation. Typical DVFS policies include rulebased [7], PID control [8] and machine learning [9]. Iqbal and John introduce a traffic aware power management technique for communication processors [10].…”