Formal online methods for voltage/frequency control in multiple clock domain microprocessors

Abstract

Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain independently.Most existing DVFS approaches are profile-based offline schemes which are mainly suitable for applications whose execution characteristics are constrained and repeatable. While some work has been published about online DVFS schemes, the prior approaches are typically heuristic-based. In this paper, we present an effective online DVFS scheme for an MCD processor which takes a formal analytic approach, is driven by dynamic workloads, and is suitable for all applications.In our approach, we model an MCD processor as a queue-domain network and the online DVFS as a feedback control problem with issue queue occupancies as feedback signals. A dynamic stochastic queuing model is first proposed and linearized through an accurate linearization technique. A controller is then designed and verified by stability analysis. Finally we evaluate our DVFS scheme through a cycle-accurate simulation with a broad set of applications selected from MediaBench and SPEC2000 benchmark suites. Compared to the best-known prior approach, which is heuristicbased, the proposed online DVFS scheme is substantially more effective due to its automatic regulation ability. For example, we have achieved a 2-3 fold increase in efficiency in terms of energy-delay product improvement. In addition, our control theoretic technique is more resilient, requires less tuning effort, and has better scalability as compared to prior online DVFS schemes.We believe that the techniques and methodology described in this paper can be generalized for energy control in processors other than MCD, such as tiled stream processors.

A Feedback-Based Approach to DVFS in Data-Flow Applications

“…The reason is that the estimation of qualityof-service (QoS) requirement is carried out on the basis of the processor utilization, which reflects the QoS requirements only indirectly. A more recent and effective approach looks in runtime at the interprocessor queues instead [4], [19], [34], [35]. In MPSoC architectures, first-in-first-out (FIFO) queues are used as data buffers between adjacent PEs in order to smooth out the effect of quick workload variations, thereby ensuring a more stable throughput rate [36].…”

Multi-Core CPU Air Cooling

“…The change in temperature is a function of temperature and the dissipated power. The dynamic voltage and frequency scaling (DVFS) is a DTM technique that changes the operating frequency of a core at run time (Wu et al, 2004). Clock Gating (CG)or stop-go technique involves freezing all dynamic operations (Donald & Martonosi, 2006).…”

Control-theoretic dynamic voltage scaling for embedded controllers

“…The approach aims to control inter-processor queue occupancy. Wu et al [16] proposed an analytic approach to DVS in multiple clock domain (MCD) processors. It is based on a dynamic stochastic queuing model and a PI (Proportional-Integral) controller with queue occupancy being the controlled variable.…”