2004
DOI: 10.1145/1037187.1024423
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Formal online methods for voltage/frequency control in multiple clock domain microprocessors

Abstract: Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain independently. Most existing DVFS approaches are profile-based offline schemes which are mainly suitable for applications whose execution char-acteristics are constrained and repeatable. While some work has been published about online DVFS schemes, the prior ap… Show more

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Cited by 23 publications
(39 citation statements)
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“…In order to obtain this number, Google Scholar [8] was used. Important practical reasons for this are that Google Scholar is freely available to anyone with an Internet connection, has better citation indexing and "Scheduling for reduced CPU energy," M. Weiser, B. Welch, A. J. Demers, and S. Shenker [11] "Automatic performance setting for dynamic voltage scaling," K. Flautner, S. Reinhardt, and T. Mudge [12] "The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction," C. Hsu and U. Kremer [13] "Energy-conscious compilation based on voltage scaling," H. Saputra "Identifying program power phase behavior using power vectors," C. Isci and M. Martonosi [18] "Live, runtime phase monitoring and prediction on real systems with application to dynamic power management," C. Isci, G. Contreras, and M. Martonosi [19] "Power and performance evaluation of globally asynchronous locally synchronous processors," A. Iyer and D. Marculescu [20] "Toward a multiple clock/voltage island design style for power-aware processors," E. Talpes and D. Marculescu [21] "Dynamic frequency and voltage control for a multiple clock domain microarchitecture," G. Semeraro, D. H. Albonesi, S. G. Dropsho, G. Magklis, S. Dwarkadas, and M. L. Scott [22] "Formal online methods for voltage/frequency control in multiple clock domain microprocessors," Q. Wu, P. Juang, M. Martonosi, and D. W. Clark [23] "Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling," G. Semeraro, G. Magklis, R. Balasubramonian, D. H. Albonesi, S. Dwarkadas, and M. L. Scott [24] "Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems," L. Yan, J. Luo, and N. K. Jha [29] Core Blocks-Pipeline-Dynamic…”
Section: List Of Selected Examplesmentioning
confidence: 99%
See 1 more Smart Citation
“…In order to obtain this number, Google Scholar [8] was used. Important practical reasons for this are that Google Scholar is freely available to anyone with an Internet connection, has better citation indexing and "Scheduling for reduced CPU energy," M. Weiser, B. Welch, A. J. Demers, and S. Shenker [11] "Automatic performance setting for dynamic voltage scaling," K. Flautner, S. Reinhardt, and T. Mudge [12] "The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction," C. Hsu and U. Kremer [13] "Energy-conscious compilation based on voltage scaling," H. Saputra "Identifying program power phase behavior using power vectors," C. Isci and M. Martonosi [18] "Live, runtime phase monitoring and prediction on real systems with application to dynamic power management," C. Isci, G. Contreras, and M. Martonosi [19] "Power and performance evaluation of globally asynchronous locally synchronous processors," A. Iyer and D. Marculescu [20] "Toward a multiple clock/voltage island design style for power-aware processors," E. Talpes and D. Marculescu [21] "Dynamic frequency and voltage control for a multiple clock domain microarchitecture," G. Semeraro, D. H. Albonesi, S. G. Dropsho, G. Magklis, S. Dwarkadas, and M. L. Scott [22] "Formal online methods for voltage/frequency control in multiple clock domain microprocessors," Q. Wu, P. Juang, M. Martonosi, and D. W. Clark [23] "Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling," G. Semeraro, G. Magklis, R. Balasubramonian, D. H. Albonesi, S. Dwarkadas, and M. L. Scott [24] "Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems," L. Yan, J. Luo, and N. K. Jha [29] Core Blocks-Pipeline-Dynamic…”
Section: List Of Selected Examplesmentioning
confidence: 99%
“…Interestingly, their online control-theoretic approach is able to achieve a full 85.5% of the EDP improvement offered by the prior off-line scheduling approach. Wu et al [23] extend the online approach using formal control theory and a dynamic stochastic model based on input-queue occupancy for the MCDs.…”
Section: Dvfs For Multiple Clock Domain Processorsmentioning
confidence: 99%
“…Based on the fact that power consumption depends on both voltage and frequency (P V DD 2 f), DVFS dynamically scales these terms to save power [6][7] [16]. Unfortunately, one of the major concerns about DVFS has been the slow off-chip voltage regulators that lack the ability to adjust to different voltages at small time scales (0.016mV / ns according to [7]). Modern real implementations are limited to temporary coarse-grained adjustments governed by runtime software (i.e., the OS).…”
Section: Background and Related Work 21 Dvfsmentioning
confidence: 99%
“…For a control process where the data is processed by a single IP core, the knowledge of input and output parameters is essential. A proportional-integral-derivative (PID) controller is the best solution in such cases [18]. But when the data is processed by hundreds of IP cores, not only the knowledge of input and output parameters, but also that of intermediate states is essential.…”
Section: Literature Review and Proposed Ideamentioning
confidence: 99%