Formal Non-fragile Verification of Step Response Requirements for Digital State-Feedback Control Systems

Abstract

We describe and evaluate a novel approach to formally verify whether a digital control system meets specifications related to step response parameters. In particular, we obtain a state feedback controller designed for a system represented by a state-space model. Then, we analyze whether its required specifications regarding settling time and maximum overshoot are met, using both open-and closed-loop forms and considering finite-word-length (FWL) effects for the latter. We developed our verification approaches inside DSVerifier, which is a verification tool that employs bounded (and unbounded) model checking based on satisfiability modulo theories. Thus, DSVerifier checks performance requirements of digital control systems considering fragility, such as round-off and numerical quantization errors. Our approaches were also evaluated over a set of standard control-system benchmarks extracted from the control literature. Experimental results show that DSVerifier can check settling time and overshoot in control systems suffering from FWL effects, while other existing approaches routinely ignore those issues. Keywords Formal verification • Digital control systems • Finite word length • Controller fragility 1 Introduction A digital control system consists of sensors, controlled systems, control algorithms, and actuators, which together seek to maintain the behavior of a plant's (controlled system) variables under control, i.e., they ensure the desired transientand steady-state responses (Franklin et al. 1998). The development of digital controllers is a crucial task in control engineering since they are routinely used for many different applications, which range from industrial plants to smart cities.

Formal synthesis of non-fragile state-feedback digital controllers considering performance requirements for step response

“…Indeed, controllers of a digital control system are heavily impaired by FWL effects 9 , as one may notice in Fig. 2 , which illustrates the block diagram of a discrete-time feedback control system, where denotes FWL effects.…”

“…Consequently, such variations can influence a system’s response and its required settling time , which could be neglected due to underestimation of FWL effects 21 , 22 . As indicated by Cavalcante et al 9 , FWL effects can be formulated as where is the discrete set of matrices composed by elements of , which can be represented in the fixed-point format , while I and F are the number of bits of integer and fractional parts, respectively. As the coefficients of K are subject to FWL effects 9 , a state-space representation can be written as where the matrix is the controller gain considering FWL effects.…”

“…Some initiatives applying formal verification to dynamic control systems have been developed 4 – 8 in the past years which includes verification methods that take into account implementation aspects and determine uncertain linear-system stability regarding digital controllers 4 , schemes that address validation of robustness at both model and code level 5 , approaches for verifying digital filters w.r.t overflow and approximation errors, due to quantization and round-off effects 6 , and controller synthesis, in an attempt to generate correct-by-construction elements 8 . Moreover, there exists also an approach that aims to formally verify whether a digital control system meets performance requirements, such as settling time and maximum overshoot, using both open- and closed-loop forms and considering FWL effects 9 . Such a work gathered on a unified framework, fragility aspects, and performance requirements, making it possible to check systems and ensure that they could be promptly deployed on real scenarios.…”

“…The CEGIS technique has two main stages, a verification step and a synthesizing one (learning step), and both are tackled here. The first step is implemented as part of another recently published work 9 and it was enhanced here by integrating a formal verification methodology into an automatic controller synthesizer as a part of our CEGIS methodology designed in the presented work. Regarding the second step, we have devised an optimization problem and then solved it using GAs to generate candidates for the associated CEGIS engine.…”

Verifying Security Vulnerabilities in Large Software Systems using Multi-Core k-Induction

“…It can automatically check both predefined safety properties (e.g., memory leaks, pointer safety, and overflows) and userdefined program assertions. It has been awarded several prizes at the International Competition on Software Verification (SV-Comp) [24] and has been applied to several domains (e.g., digital controllers [25], photovoltaic systems [26]). Nonetheless, as a bounded model checker, it is susceptible to resource exhaustion problems, and scaling up BMC tools to handle large software is an open problem.…”