Formal model and code verification in Model-Based Design

Popovici, Katalin; Lalo, Marc

doi:10.1109/newcas.2009.5290500

Cited by 10 publications

(10 citation statements)

References 5 publications

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“…Furthermore, we classified six articles into the subcategory "analysis of properties" [3,10,11,18,20,33], as those papers concentrate on specific quality properties to be addressed with analysis techniques. For example, Farkas and Grund [33] present an approach that checks custom rules, industry standards, and enterprise-wide guidelines.…”

Section: Discussionmentioning

confidence: 99%

“…Furthermore, the model-based framework INProVE supports definition of quality metrics [18] that can be checked automatically. Popovici and Lalo [20] describe an approach that checks properties of a model and proves the absence of certain run-time errors.…”

Section: Discussionmentioning

confidence: 99%

“…18 papers consider analysis, 19 papers describe test techniques applied to Matlab Simulink models, and 7 papers present combinations. 41% analysis test [3,8,10,11,16,17,18,19,20,21,22,23,24,25,29,33 Figure 4 shows the publication years of the result set. It can be seen that none of the relevant publications was published before 2000, and that 75% of the papers were published in the last five years.…”

Section: Rq1: Classification Of Approachesmentioning

confidence: 99%

“…tool tool chain [8,9,18,19,37] 5 10 15 20 [14, 32, 40] 25 [12] tool overview commercial tool prototype tool [4,15,20,27,28,29] [2, 3,5,6,10,11,12,13,16,21,23,24,26,31,33,34,35,36,38,39,41,42,43,44] …”

Section: Rq2: Tool Supportmentioning

confidence: 99%

See 3 more Smart Citations

Analysis and testing of matlab simulink models: a systematic mapping study

Elberzhager

Rosbach

Bauer

2013

Proceedings of the 2013 International Workshop on Joining AcadeMiA and Industry Contributions to Testing Automation

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Matlab Simulink is one of the major modeling and simulation tools applied in different embedded systems domain. Quality assurance is an essential, but often highly effort-consuming part of software development. A lot of different quality assurance techniques exist to ensure high quality, but these analysis and testing techniques are often applied in isolation. Therefore, we are interested in synergy effects when applying them in combination. Consequently, we performed a systematic mapping study to identify the current state of the art regarding such quality assurance techniques and existing combinations. Our main result is a classification of existing quality assurance techniques applied on Matlab Simulink models, and an overview of existing tool support and the validity of the approaches.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Rq1: Classification Of Approachesmentioning

confidence: 99%

Section: Rq2: Tool Supportmentioning

confidence: 99%

See 2 more Smart Citations

Analysis and testing of matlab simulink models: a systematic mapping study

Elberzhager

Rosbach

Bauer

2013

Proceedings of the 2013 International Workshop on Joining AcadeMiA and Industry Contributions to Testing Automation

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“…Much effort has been put into creating embedded system development environments that promote the early detection of bugs through formal verification [41][45] [46] [47]. In these approaches, a system must be represented at the correct level of abstraction to reduce complexity for the model checker, a problem to which many solutions have been proposed [44].…”

Section: Practical Integration Of Simulation and Early Formal Verificmentioning

confidence: 99%

Exploring formal verification methodology for FPGA-based digital systems.

Hu¹

2012

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With the Life Extension Programs (LEPs), many nuclear weapon (NW) analog electronic components are being replaced by modern digital devices, increasing system complexities dramatically. Ensuring the reliability, security, and robustness of these upgraded systems is critically important. Many custom hardware systems throughout the NW operations space rely on Field-Programmable Gate Arrays (FPGAs) to implement sophisticated logic. Effective verification, while increasing confidence, can reduce the overall effort in system debugging and testing. This work explored Formal Verification (FV) of trusted FPGA-based hardware designs through the use of novel algorithms. The algorithms developed support the analysis of critical digital components, such as memory, with mathematical reasoning from automated theorem proving and model checking. Such verification will detect race conditions and corner cases at an early stage, eliminating system failure and instability during operation.

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