Formal hardware verification by symbolic ternary trajectory evaluation

Bryant, Randal E.; Seger, C.-J.H.; Beatty, Derek L.

doi:10.1145/127601.127701

Cited by 72 publications

(32 citation statements)

References 6 publications

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“…This arrangement gives STE a native capability for partitioned Boolean abstraction that, by the method known as symbolic indexing [12], can be very effective on large but 'semantically regular' datapaths. A full discussion of symbolic indexing and its automation can be found in [13] and [14].…”

Section: B Ste Verification and The Translation Problemmentioning

confidence: 99%

Assume-guarantee validation for STE properties within an SVA environment

Khasidashvili

Gavrielov

Melham

2009

2009 Formal Methods in Computer-Aided Design

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Abstract-Symbolic Trajectory Evaluation is an industrialstrength verification method, based on symbolic simulation and abstraction, that has been highly successful in data path verification, especially microprocessor execution units. These correctness results are typically obtained under certain assumptions about how the verified hardware block's inputs are driven, as well as assumptions about the values of these inputs. For correct overall operation, the hardware environment within which the verified block resides is expected to satisfy these assumptions.We describe a translation of these proof assumptions into System Verilog Assertions. These are then used as checkers in dynamic validation of the hardware environment within which blocks verified by Symbolic Trajectory Evaluation operate. The result is a pragmatic assume-guarantee method that increases the quality and confidence in verification results, requires little or no modification to the Symbolic Trajectory Evaluation proofs, and leverages pre-existing dynamic validation infrastructure.

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Section: B Ste Verification and The Translation Problemmentioning

confidence: 99%

Assume-guarantee validation for STE properties within an SVA environment

Khasidashvili

Gavrielov

Melham

2009

2009 Formal Methods in Computer-Aided Design

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“…If this non-determinism is represented using the ternary value A", then it is possible to construct a single trajectory model [11]. The key property of a single trajectory model is that for a given input stream, only one sequence of output transitions is possible.…”

Section: Single Trajectory Delay Modelsmentioning

confidence: 99%

Trace Algebra for Automatic Verification of Real-Time Concurrent Systems

Burch¹

1992

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“…STE is an extension of symbolic simulation that has been used to formally verify circuits, including a simple pipelined data path [3]. Incorporation of the EMM in STE enabled the verification of the pipelined data path with a significantly larger register file than previously possible.…”

Section: Introductionmentioning

confidence: 99%

Efficient modeling of memory arrays in symbolic ternary simulation

Velev

Bryant

1998

Tools and Algorithms for the Construction and Analysis of Systems

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Abstract. This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variables used to characterize the initial state of the memory is proportional to the number of distinct symbolic memory locations accessed. The behavioral model provides a conservative approximation of the replaced memory array, while allowing the address and control inputs of the memory to accept symbolic ternary values. Memory state is represented by a list of entries encoding the sequence of updates of symbolic addresses with symbolic data. The list interacts with the rest of the circuit by means of a software interface developed as part of the symbolic simulation engine. This memory model was incorporated into our verification tool based on Symbolic Trajectory Evaluation. Experimental results show that the new model significantly outperforms the transistor level memory model when verifying a simple pipelined data path.

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Formal hardware verification by symbolic ternary trajectory evaluation

Cited by 72 publications

References 6 publications

Assume-guarantee validation for STE properties within an SVA environment

Assume-guarantee validation for STE properties within an SVA environment

Trace Algebra for Automatic Verification of Real-Time Concurrent Systems

Efficient modeling of memory arrays in symbolic ternary simulation

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