Formal Hardware/Software Co-verification of Application Specific Instruction Set Processors

Loitz, Sacha; Wedler, Markus; Stoffel, Dominik; Brehm, Christian; Kunz, Wolfgang; Wehn, Norbert

doi:10.1007/978-1-4614-1427-8_1

Cited by 2 publications

(2 citation statements)

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“…Separate proofs of hardware and software correctness are often not sufficient to assess the overall behavior of the embedded system. This problem increases as the borderline between hardware and software is becoming blurred in highly optimized application-specific designs where the semantics of a program are sometimes only defined in a specific hardware context [1]. In this paper, we propose a computational model that can be used to integrate low-level software verification into SAT-based hardware verification environments, thus allowing for verifying low-level software in its particular hardware environment.…”

Section: Introductionmentioning

confidence: 99%

A computational model for SAT-based verification of hardware-dependent low-level embedded system software

Schmidt

Villarraga

Bormann

et al. 2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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This paper describes a method to generate a computational model for formal verification of hardware-dependent software in embedded systems. The computational model of the combined HW/SW system is a program netlist (PN) consisting of instruction cells connected in a directed acyclic graph that compactly represents all execution paths of the software. The model can be easily integrated into SAT-based verification environments such as those based on Bounded Model Checking (BMC). The proposed construction of the model, however, allows for an efficient reasoning of the SAT solver over entire execution paths. We demonstrate the efficiency of our approach by presenting experimental results from the formal verification of an industrial LIN (Local Interconnect Network) bus node, implemented as a software driver on a 32-bit RISC machine.

show abstract

Section: Introductionmentioning

confidence: 99%

A computational model for SAT-based verification of hardware-dependent low-level embedded system software

Schmidt

Villarraga

Bormann

et al. 2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

View full text Add to dashboard Cite

show abstract

“…Separate proofs of hardware and software correctness are often not sufficient to assess the overall behavior of the embedded system. This problem increases as the borderline between hardware and software is becoming blurred in highly optimized application-specific designs where the semantics of a program are sometimes only defined in a specific hardware context [1]. In this paper, we propose a computational model that can be used to integrate low-level software verification into hardware verification environments, thus allowing for verification of low-level software in its particular hardware environment.…”

Section: Introductionmentioning

confidence: 99%

A New Formal Verification Approach for Hardware-dependent Embedded System Software

Schmidt

Villarraga

Fehmel

et al. 2013

IPSJ Transactions on System LSI Design Methodology

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This paper describes a method to generate a computational model for formal verification of hardwaredependent software in embedded systems. The computational model of the combined HW/SW system is a program netlist (PN) consisting of instruction cells connected in a directed acyclic graph that compactly represents all execution paths of the software. The model can be easily integrated into SAT-based verification environments such as those based on Bounded Model Checking (BMC). The proposed construction of the model allows for an efficient reasoning of the SAT solver over entire execution paths. Program netlists are compositional. The paper presents how they can be combined to model interrupt-driven systems. We demonstrate the efficiency of our approach by presenting experimental results from the formal verification of an industrial LIN (Local Interconnect Network) bus node, implemented as a software driver on a 32-bit RISC machine.

show abstract

Formal Hardware/Software Co-verification of Application Specific Instruction Set Processors

Cited by 2 publications

References 10 publications

A computational model for SAT-based verification of hardware-dependent low-level embedded system software

A computational model for SAT-based verification of hardware-dependent low-level embedded system software

A New Formal Verification Approach for Hardware-dependent Embedded System Software

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