Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology

Amin, Najam Muhammad; Wang, Zhigong; Li, Zhiqun

doi:10.1631/jzus.c1400087

Cited by 2 publications

(3 citation statements)

References 18 publications

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“…This work is a continuation of our work in Reference [1], where a folded down-conversion mixer, incorporated at the final down-conversion stage of a 60 GHz receiver, was presented. The dual conversion receiver architecture with the focus of this work highlighted is shown in Figure 1.…”

Section: Introductionmentioning

confidence: 84%

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

Amin

Wang

et al. 2015

J. Semicond.

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This paper presents the design of a low power (LP) and a low noise figure (NF) quadrature demodulator with an on-chip frequency divider for quadrature local oscillator (LO) signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demodulator is designed for an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency (IF) band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain (VCG) ranging from 14.2 to 13.2 dB, and a minimum single-sideband NF (SSB-NF) of 9 dB. The measured third-order input intercept point (IIP3) is −3.3 dBm for a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-nm LP CMOS technology, are also presented in this paper.

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Section: Introductionmentioning

confidence: 84%

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

Amin

Wang

et al. 2015

J. Semicond.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Recently, many fine papers about mixers have appeared (e.g., [15,16]). The difference between those papers and this one is that our intention is to provide an overview based on agreement of analysis and measurement results.…”

Section: Advances In Electrical Engineeringmentioning

confidence: 99%

“…In References, our intention was to obtain original ones; however, a foundation work [1] and some most recent mixer papers [15,16] are also included. Figures 7(a) and 7(b).…”

Section: Advances In Electrical Engineeringmentioning

confidence: 99%

Comparison of 6 Diode and 6 Transistor Mixers Based on Analysis and Measurement

Ladvánszky

Osbath

2016

Advances in Electrical Engineering

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Our goal is to overview semiconductor mixers designed for good large signal performance. Twelve different mixers were compared utilizing pn diodes, bipolar transistors, and/or junction field effect transistors. The main aspect of comparison is the third-order intercept point (IP3), and both circuit analysis and measurement results have been considered. IP3 has been analyzed by the program AWR (NI AWR Design Environment) and measured by two-tone test (Keysight Technologies). We provide three ways of improvement of large signal performance: application of a diplexer at the RF port, reduction of DC currents, and exploiting a region of RF input power with infinite IP3. In addition to that, our contributions are several modifications of existing mixers and a new mixer circuit (as illustrated in the figures). It is widely believed that the slope of the third-order intermodulation product versus input power is always greater than that of the first-order product. However, measurement and analysis revealed (as illustrated in the figures) that the two lines may be parallel over a broad range of input power, thus resulting in infinite IP3. Mixer knowledge may be useful for a wide range of readers because almost every radio contains at least one mixer.

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Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology

Cited by 2 publications

References 18 publications

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

Comparison of 6 Diode and 6 Transistor Mixers Based on Analysis and Measurement

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