Fly-Over: A Light-Weight Distributed Power-Gating Mechanism for Energy-Efficient Networks-on-Chip

Boyapati, Rahul; Huang, Jifu; Wang, Ningyuan; Kim, Kyung Hoon; Yum, Ki Hwan; Kim, Eun Jung

doi:10.1109/ipdps.2017.77

Cited by 11 publications

(2 citation statements)

References 31 publications

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“…Existing NoCs mainly adopt wormhole/virtual channel routers, which include buffers at every input port to improve the bandwidth efficiency in case of packet contention [6,7]. However, using of buffers consumes a significant amount of chip area and static power [8,9], and it is also challenging to maintain efficient utilization of buffers under different workloads [10].…”

Section: Introductionmentioning

confidence: 99%

UBMR:A low-power and low-area multicastrouter with unified buffers forNetwork-on-Chips

Ouyang,

wang,

et al. 2024

Preprint

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Network-on-Chip(NoC) has become a promising communicationparadigm for Multi-Processors System-on-Chip (MPSoC) due to its highcommunication efficiency, good scalability, and high reliability. In prac-tice, in addition to one-to-one unicast traffic in NoC, there is also a largeamount of one-to-many multicast traffic. The traditional unicast-basedmechanism for handling multicast traffic leads to a large number of repet-itive and redundant packets in the network, which rapidly consumes thenetwork bandwidth and dramatically reduces the performance of the net-work. Meanwhile, with the continuous scaling of the chip fabrication pro-cess, the power consumption increases dramatically, which also makes theNoC design face great challenges. To mitigate these problem, we proposea tree-based multicast routing algorithm to ensure that multicast pack-ets and their copies reach the destination router all through the shortestpath. For better compatibility with our proposed routing algorithm, wealso propose a unified buffer multicast router architecture, which not onlysimplifies the multicast routing algorithm, but also reduces the powerconsumption and the area overhead of the router. Detailed simulationresults show that the number of packets transmitted in the networkis reduced by 28%, and the area and power consumption are reducedby 40.6% and 38.6%, respectively, compared to conventional routers.

show abstract

Section: Introductionmentioning

confidence: 99%

UBMR:A low-power and low-area multicastrouter with unified buffers forNetwork-on-Chips

Ouyang,

wang,

et al. 2024

Preprint

View full text Add to dashboard Cite

show abstract

“…Router power is distributed among the buffers and other components, of which buffers are known to consume 45% of the total router power. Several attempts have been made to reduce the power of NoC routers [10–12]. In the context of dark silicon, the on‐chip traffic distribution is not uniform and there could be portions on the chip which have very less traffic.…”

Section: Introductionmentioning

confidence: 99%

Write‐variation aware alternatives to replace SRAM buffers with non‐volatile buffers in on‐chip interconnects

Rani

Kapoor

2019

IET Computers & Digital Techniques

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Architectures for Self-Powered Edge Intelligence

Trivedi

Kung

2022

Handbook of Computer Architecture

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Fly-Over: A Light-Weight Distributed Power-Gating Mechanism for Energy-Efficient Networks-on-Chip

Cited by 11 publications

References 31 publications

UBMR:A low-power and low-area multicastrouter with unified buffers forNetwork-on-Chips

UBMR:A low-power and low-area multicastrouter with unified buffers forNetwork-on-Chips

Write‐variation aware alternatives to replace SRAM buffers with non‐volatile buffers in on‐chip interconnects

Architectures for Self-Powered Edge Intelligence

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