2003
DOI: 10.1109/tasc.2003.813890
|View full text |Cite
|
Sign up to set email alerts
|

FLUX-1 RSFQ microprocessor: Physical design and test results

Abstract: The Flux-1 chip is an RSFQ implementation of a small general-purpose processing engine with target clock frequency of 20 GHz and over 5000 gates (over 60K Josephson junctions) connected in an irregular pattern. The scale of this design task forced us to re-think conventional RSFQ design methodology and implement new approaches suitable for digital systems of this level of complexity and beyond. This paper presents lessons learned from the Flux-1 effort, mostly concentrating on chip physical design. Here we dis… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
27
0

Year Published

2003
2003
2023
2023

Publication Types

Select...
7
3

Relationship

0
10

Authors

Journals

citations
Cited by 52 publications
(27 citation statements)
references
References 9 publications
(5 reference statements)
0
27
0
Order By: Relevance
“…1 and 4) in contrast to the design methods reported in [5] and [6]. By doing so, we avoid using explicit PTL-connectable splitters which would add three more JJs (corresponding to a driver-receiver pair) for each signal splitting.…”
Section: A Ptl-connectable Logic Cell and Circuit Design Methodsmentioning
confidence: 99%
“…1 and 4) in contrast to the design methods reported in [5] and [6]. By doing so, we avoid using explicit PTL-connectable splitters which would add three more JJs (corresponding to a driver-receiver pair) for each signal splitting.…”
Section: A Ptl-connectable Logic Cell and Circuit Design Methodsmentioning
confidence: 99%
“…nonsuperconductive connection middle-scale RSFQ devices have been reported up to now operating at clock frequencies of only few tens GHz (Bunyk et al, 2003;Tanaka et al, 2007). The big gap between the speed performance of the simple and the middle-scale RSFQ digital devices is tightly connected to the complicated global clock distribution network of the complex synchronous RSFQ digital circuits.…”
Section: Basics Of the Rsfq Digital Electronicsmentioning
confidence: 99%
“…Although this characteristic of the SFQ logic circuits makes it suitable for deep pipelining [6], designers of the SFQ circuits are required to adjust the timing of signals and clock inputs to all logic gates very precisely. The precision of the clock supplied to all logic gates is particularly important, and sophisticated clocking schemes for the SFQ logic circuits have been developed to optimally design high-speed SFQ logic circuits [7]. Because of these reasons, there are only a few professional designers who can design large-scale SFQ logic circuits.…”
Section: Introductionmentioning
confidence: 99%