Floorplanning for Area Optimization Using Parallel Particle Swarm Optimization and Sequence Pair

Prakash, Atul; Lal, Ram A.

doi:10.1007/s11277-020-08015-5

Cited by 8 publications

(3 citation statements)

References 25 publications

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“…As a result, the MOFO-FP technology was suggested, which minimizes energy usage, wire length, and heat output. In Prakash and Lal (2021) to solve the floor planning issue, researchers created a metaheuristic strategy known as P-PSO. The P-PSO explores the search space for an optimum solution using a novel "greedy operation" on the SP.…”

Section: Related Workmentioning

confidence: 99%

“…The aspect ratio, as well as the IO architecture, is considered while designing the floors (Shunmugathammal et al 2020b) (Giorgini et al 2018;Wang et al 2020;Sadeghi et al 2020). If the floor plan would be of poor quality, there's also a risk of routing bottleneck and dying area wastage (Prakash and Lal 2021). As the available resources of routing are restricted, velocity and area are the critical computational factors to be taken into account.…”

Section: Introductionmentioning

confidence: 99%

“…This specifies the positions and size of modules upon the chip to maximize the chip's surface area. One key limitation to considering the locations of the modules is that there's no overlapping between two modules (Sivaranjani and Senthil Kumar 2015;Shunmugathammal et al 2020a;Srinivasan and Venkatesan 2021;Prakash and Lal 2021). To deal with the rising complexity of architecture, hierarchical and IPbased components are utilized, making floor planning throughout the VLSI design cycle is increasingly realistic.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization

Pondreti

Kaparapu

2023

International Journal of Swarm Intelligence Research

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Floor planning is indeed an obvious design process in VLSI physical layout since it specifies the dimensions, structure, as well as positions of components upon the chip; in addition, information regarding the overarching silicon area, interlinks, and latency is also provided. VLSI floor planning is an NP-hard issue as the floor plan representations are a crucial component in this process. The intricacy, as well as solution space of the floor plan layout, is influenced by the floorplan visualizations. To tackle the VLSI floor plan challenge, numerous researchers have developed numerous meta-heuristic optimization techniques. The main objective of this work presents a novel multi-objective hybrid optimization method for solving the floor plan optimization issue. Standard DOX and ALO are conceptually combined in the proposed hybrid optimization referred to as Dingo Updated Ant Lion Optimization (DUALO) model. The multi-objectives like wire length, area, and penalty function are taken into consideration.

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Section: Related Workmentioning

confidence: 99%