Floating Gate super multi level NAND Flash Memory Technology for 30nm and beyond

Kamigaichi, T.; Arai, F.; Nitsuta, H.; Endo, Masamori; Nishihara, K.; Murata, Takahiro; Takekida, H.; Izumi, T.; Uchida, Ken; Maruyama, Toru; Kawabata, I.; Suyama, Y.; Sato, Akira; Ueno, Katsunori; Takeshita, Hiroaki; Joko, Y.; Watanabe, Soichi; Liu, Y.; Meguro, H.; Kajita, Akihiro; Ozawa, Yoshio; Watanabe, T.; Sato, Shigeo; Tomiie, H.; Kanamaru, Y.; Shoji, R.; Lai, Chun‐Hung; Nakamichi, M.; Oowada, K.; Ishigaki, Takashi; Hemink, G.; Dutta, Debasree; Yan, Dong; Chen, C.; Liang, Guanfeng; Higashitani, M.; Lutze, J.

doi:10.1109/iedm.2008.4796825

Cited by 10 publications

(4 citation statements)

References 1 publication

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“…This V th increase of 1 V is about 0.5 V-larger than that of the conventional NAND EEPROM of similar dimensions. 6) This result suggest that more defect remain in the channel region of the self-manufactured SOI substrate used by D-ToPS than that of the production grade Si substrate used by the conventional NAND EEPROM. More carrier trap centers are therefore generated in the tunnel oxide, and a certain amount of carriers are captured.…”

Section: Resultsmentioning

confidence: 96%

Depletion-Type Cell-Transistor on Partial Silicon-on-Insulator Substrate for 2× nm Generation Floating-Gate NAND Electrically Erasable Programmable Read Only Memory

Mizukami

Nishihara

Ishida

et al. 2010

Jpn. J. Appl. Phys.

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A new effect has been observed at low temperatures when conduction is restricted to two dimensions in an n-type GaAs impurity band. When the carrier concentration is less than 10" cm-2 the conductance is found to oscillate as a function of carrier concentration. The oscillations can be resolved into simple series with the minima periodic functions of the mean electron separation. Suppression of the main series and enhancement of a subsidiary series is achieved by increasing the electric field responsible for transport; this results in differential negative resistance at certain carrier concentrations. The effect may possibly arise from, an ordering of the electrons by Coulomb repulsion, although it is difficult to envisage how this can happen in a random array of donors and we have at present no model to explain the effect.

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Section: Resultsmentioning

confidence: 96%

Depletion-Type Cell-Transistor on Partial Silicon-on-Insulator Substrate for 2× nm Generation Floating-Gate NAND Electrically Erasable Programmable Read Only Memory

Mizukami

Nishihara

Ishida

et al. 2010

Jpn. J. Appl. Phys.

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“…The result in Fig. 9 is only due that the program voltage to adjust the same Vth is decreased as the P/E cycle is progressed [8]. After 100 P/E Cycle and 1000 P/E Cycle, the program speed is faster 0.3V and 0.5V, respectively, than the initial program speed.…”

Section: Discussionmentioning

confidence: 94%

New scaling limitation of the floating gate cell in NAND Flash Memory

Kim

Lee

et al. 2010

2010 IEEE International Reliability Physics Symposium

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As the scaling in NAND Flash Memory is progressed, the various interferences among the adjacent cells are more and more increased and the new phenomenon which is ignored until now has to be considered. In this paper, we will introduce the new program interference phenomenon which is generated between the program word line and the adjacent word lines along the bit-line. This new program interference is that the Vth's of the adjacent word lines along the bit-line are decreased while a word line is programming. Because this phenomenon is severely aggravated as the gate space is decreased, we have to consider this program interference for the future technology nodes.

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“…Nevertheless, NVM devices based on floating-gate (FG) concept are still very attractive for their performances and reliability at high temperatures despite some scaling-limiting factors like the high voltages required for program/erase (P/E) operations [3]. High-k interpoly dielectrics (IPDs) have been introduced to increase FG to control-gate (CG) coupling [4], thus allowing to reduce P/E voltages.…”

Section: Introductionmentioning

confidence: 99%

A Technique to Extract High-$k$ IPD Stack-Layer Thicknesses From $C$– $V$ Measurements

Larcher

Pavan

Padovani

et al. 2009

IEEE Electron Device Lett.

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We propose in this letter a simple technique based on C-V measurements which allows the estimating of the thicknesses of SiO X and high-k layers of interpoly dielectric (IPD) stacks. We apply this technique to IPD Al 2 O 3 -based stacks for floating-gate memory applications, finding a good agreement with TEM measurements. In addition, simulation results are provided to demonstrate the correctness of the basic assumption of this technique.

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Floating Gate super multi level NAND Flash Memory Technology for 30nm and beyond

Cited by 10 publications

References 1 publication

Depletion-Type Cell-Transistor on Partial Silicon-on-Insulator Substrate for 2× nm Generation Floating-Gate NAND Electrically Erasable Programmable Read Only Memory

Depletion-Type Cell-Transistor on Partial Silicon-on-Insulator Substrate for 2× nm Generation Floating-Gate NAND Electrically Erasable Programmable Read Only Memory

New scaling limitation of the floating gate cell in NAND Flash Memory

A Technique to Extract High-$k$ IPD Stack-Layer Thicknesses From $C$– $V$ Measurements

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