Floating Gate-Based Field Programmable Mixed-Signal Array

Wunderlich, Richard B.; Adil, Farhan; Hasler, P.

doi:10.1109/tvlsi.2012.2211049

Cited by 41 publications

(16 citation statements)

References 21 publications

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“…The STLS are modified EEPROM devices, fabricated in a standard CMOS process, that simultaneously provide long-term storage (non-volatile), computation, and adaptation in a single device. The development of Large-Scale Field Programmable Analog Arrays (FPAA) enabled configuration to be used for physically based neuromorphic techniques (Twigg et al, 2007; Basu et al, 2010a,b; Schlottmann et al, 2010, 2012a,b, c; Wunderlich et al, 2012). These approaches allow the added advantage of those building applications not to have expertise in IC design, a separation that should prove useful for the neuromorphic community as well.…”

Section: Large-scale Neuromorphic Systemsmentioning

confidence: 99%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

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Section: Large-scale Neuromorphic Systemsmentioning

confidence: 99%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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“…Analog or digital signals can be routed on the same fabric [1] and can be used by CABs or CLBs. Early attempts at these approaches were considered earlier [36,37]. Why would one take this approach?…”

Section: Digital Computationmentioning

confidence: 99%

Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

Hasler

2017

JLPEA

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Abstract:The focus of this work is to develop a starting framework for analog numerical analysis and related algorithm questions. Digital computation is enabled by a framework developed over the last 80 years. Having an analog framework enables wider capability while giving the designer tools to make reasonable choices. Analog numerical analysis concerns computation on physical structures utilizing the real-valued representations of that physical system. This work starts the conversation of analog numerical analysis, including exploring the relevancy and need for this framework. A complexity framework based on computational strengths and weaknesses builds from addressing analog and digital numerical precision, as well as addresses analog and digital error propagation due to computation. The complimentary analog and digital computational techniques enable wider computational capabilities.

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“…To effectively utilize wake-up in wireless sensor platforms, a flexible form of custom low-power signal processing hardware is desired. Given the advantages of ultra-low-power analog circuitry described above, we are seeking to simplify the process of analog circuit design by leveraging the growing field of reconfigurable analog systems [8,15,17]. Much like the all-digital field-programmable gate arrays (FPGAs) that have enabled rapid prototyping of digital systems, fieldprogrammable analog arrays (FPAAs) seek to bring that same flexibility and reconfigurability to analog designs.…”

Section: Related Workmentioning

confidence: 99%

“…In this work, we present a reconfigurable analog/mixedsignal platform (RAMP) that extends the concept of an FPAA into both the analog and digital domains. While some recent work has investigated the use of mixed-signal design within FPAAs [5,17], they have been largely restricted to applications in data converters and digitally-assisted analog circuits. Instead, our RAMP has been designed specifically with low-power wireless sensing applications in mind, and as a result, it is able to provide a large assortment of analog and mixed-signal routines for signal conditioning, signal classification, event detection, and wake-up generation.…”

Section: Related Workmentioning

confidence: 99%

Ramp

Kelly

Rumberg

Graham

et al. 2015

Proceedings of the 14th International Conference on Information Processing in Sensor Networks

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The requirements of many wireless sensing applications approach, or even exceed, the limited hardware capabilities of energy-constrained sensing platforms. To achieve such demanding requirements, some sensing platforms have included low-power application-specific hardware-at the expense of generality-to pre-process the sensor data for reduction to only the relevant information. While this additional hardware can save power by reducing the activity of the microcontroller and radio, a unique hardware solution is required for each application, which presents an unrealistic burden in terms of design time, cost, and ease of integration. To diminish these burdens, we present a reconfigurable analog/mixed-signal sensing platform in this work. At the hardware-level, this platform consists of a reconfigurable integrated circuit containing many commonly used signal-processing blocks and circuit components that can be connected in any configuration. At the software level, this platform provides a framework for abstracting this underlying hardware. We demonstrate how to quickly develop new applications on this platform, ranging from standard sensor interfacing techniques to more complicated intelligent pre-processing and wake-up detection. We also demonstrate how to integrate this platform with commonly used wireless sensor nodes and embedded-system platforms.

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Floating Gate-Based Field Programmable Mixed-Signal Array

Cited by 41 publications

References 21 publications

Finding a roadmap to achieve large neuromorphic hardware systems

Finding a roadmap to achieve large neuromorphic hardware systems

Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

Ramp

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