Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview

Surkanti, Punith R.; Garimella, Annajirao; Furth, Paul M.

doi:10.1109/vlsid.2018.68

Cited by 12 publications

(4 citation statements)

References 28 publications

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“…Flipped Voltage Follower based LDOs (FVF LDOs) are capable of providing high bandwidth and by that, increased PSRR due to presence of fast local loop [19]. They have been of special interest in recent years as they do not require external capacitors [19]- [23]. The FVF LDO that is used in this work is shown in Fig.…”

Section: Circuit Under Test: Fvf Ldomentioning

confidence: 99%

Low-Cost Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Enhanced Time-Efficiency

Saikiran

Sekyere

Ganji

et al. 2022

Preprint

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Defect-oriented testing is becoming increasingly popular in recent times, especially in safety-critical applications in automotive, space and medical industries. The stringent quality requirements from these industries such as zero defective parts per million (DPPM) necessities a need to have efficient defect testing methods. Furthermore, the overall development time of integrated circuit can be reduced by reducing the defect simulation time. In this work, we present a simple and time-efficient defect simulation framework for pre-silicon testing of AMS circuits. In our method, a given defect model is realized using Verilog-A modules and tests multiple defects in a circuit in a single-run simulation. In contrast to the conventional defect simulation framework, our method saves simulation time by avoiding the repetitive work of generating a netlist for each defect and by reducing the time overhead for the simulator to interface with data/file-handling system. To strongly validate our proposed framework, we use diverse AMS circuits such as operational amplifier (op amp), fast transient flipped-voltage follower based low-dropout regulator (FVF LDO) and Successive-approximation-register (SAR) analog-to-digital converters (ADC). For DC testing schemes used for op amp and LDO testing, we show that our proposed framework reduces the simulation time to less than one-tenth (1/10th) in comparison with conventional framework. On the other hand, for the transient testing scheme, the proposed framework reduces the simulation time to less than 50% of the conventional framework. Furthermore, we also show that there is no negative impact on the defect coverage using the proposed framework.

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Section: Circuit Under Test: Fvf Ldomentioning

confidence: 99%

Low-Cost Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Enhanced Time-Efficiency

Saikiran

Sekyere

Ganji

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…However, the low loop gain of the FVF structure affects the response time, line regulation and load regulation in the stable output state [8,27,28]. The FVF structure can be replaced by a folded FVF structure [25,[29][30][31][32], as illustrated in Figure 1b. With the addition of cascade transistor M 2 in the feedback loop, the loop gain of the folded FVF is improved.…”

Section: Introductionmentioning

confidence: 99%

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

Chen

Wang

et al. 2022

Electronics

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The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.

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“…extending the bandwidth of the error amplifier by changing its configuration [13], [14]; IV. providing a lower impedance pass transistor stage to extend the loop bandwidth [15]- [17]. But the approach I usually needs extra current passes which increase quiescent current and large filter components.…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low Quiescent Current LDO with FVF-Based Load Transient Enhanced Circuit

Mii

Nagahama

Watanabe

2020

IEICE Trans. Electron.

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This paper proposes an ultra-low quiescent current lowdropout regulator (LDO) with a flipped voltage follower (FVF)-based load transient enhanced circuit for wireless sensor network (WSN). Some characteristics of an FVF are low output impedance, low voltage operation, and simple circuit configuration [1]. In this paper, we focus on the characteristics of low output impedance and low quiescent current. A load transient enhanced circuit based on an FVF circuit configuration for an LDO was designed in this study. The proposed LDO, including the new circuit, was fabricated in a 0.6 μm CMOS process. The designed LDO achieved an undershoot of 75 mV under experimental conditions of a large load transient of 100 μA to 10 mA and a current slew rate (SR) of 1 μs. The quiescent current consumed by the LDO at no load operation was 204 nA.

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Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview

Cited by 12 publications

References 28 publications

Low-Cost Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Enhanced Time-Efficiency

Low-Cost Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Enhanced Time-Efficiency

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

Ultra-Low Quiescent Current LDO with FVF-Based Load Transient Enhanced Circuit

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