Flip-flops soft error rate evaluation approach considering internal single-event transient

Song, Ruiqiang; Chen, Shuming; He, Yuhui; Du, Yi

doi:10.1007/s11432-014-5260-z

Cited by 15 publications

(8 citation statements)

References 19 publications

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“…Moreover, the MSIFF is also capable to mitigate SEU induced by the internal single-event transient (SET) [22,23]. SET pulses generated at the sensitive nodes may be captured and cause SEU if the latch is from transparent state to latched state.…”

Section: Hardness Mechanism Of the Msiffmentioning

confidence: 99%

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

Song

Shao

Liang

et al. 2020

IEICE Electron. Express

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This paper presents a radiation-hardened flip-flop called MSIFF. The sensitive node-pairs between the master and slave latches are readjusted at layout-level. It obtains a high SEU tolerance with slight area and performance degradation. A test chip was irradiated with the static and dynamic test modes to validate the SEU tolerance of the proposed MSIFF. Experimental results demonstrate superior performance of the MSIFF over the conventional DICE and D flip-flop.

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Section: Hardness Mechanism Of the Msiffmentioning

confidence: 99%

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

Song

Shao

Liang

et al. 2020

IEICE Electron. Express

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“…The basic sampling, keeper circuit, and C-element parts are used to implement the hybrid FF. From related works [25][26][27][28][29][30][31][32][33][34][35], authors have focused to discuss the SEE effects only, another solution is C-element, which is proposed in [35] to overcome the SEE effects such as SET, and SEU in hybrid FF design. The hybrid pulsed FF, using C-element as a fundamental stage, provides better result to resist switching activity and improves data activity.…”

Section: Problem Definitionmentioning

confidence: 99%

Low power radiation aware transistor level design using tri‐state inverter embedded non‐clock gating technique

Kamalakannan¹,

Venkatachalam²

2019

IET Circuits, Devices & Systems

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The effect of radiation on digital circuits in particularly complementary metal oxide semiconductor (CMOS) technology has been known since many years. The two most important radiation effects are total ionisation dose and single-event effects (SEEs). The complexity of circuit will increase depends on the number of gate inputs, which degrades the radiation to accelerate the total dose levels. The incremental dose level affects the circuit parameter failure, which affects the functionality of logic design. Many authors focus to reduce radiation effects with avoid function loss, but those extra efforts consume more power. In this study, a low power radiation aware circuit design is proposed. First, the physics-based modelling approach is used for compute radiation response of each component in the circuit. Tri-state inverter embedded non-clocked gating technique is proposed to eliminate unwanted latches and disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals. For simulation purpose, the authors applied their proposed technique in flip-flops and make it as more aware of radiation effects and power consumption. The performance of the proposed circuit design is analysed at 16 nm CMOS predictive technology model in terms of power delay product using HSPICE tool.

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“…In our previous works, TCAD simulation was a useful means to investigate the physical mechanism of single-event effect (SEE) [10,11,12]. In this paper, TCAD simulation was performed to compare the SEU sensitivity of the DICE flip-flop with two layout topologies.…”

Section: Simulation Setupmentioning

confidence: 99%

Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop

Cai

Chen

2017

IEICE Electron. Express

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This paper studies the impact of adjacent transistors on the SEU sensitivity of the DICE flip-flop. We compare the SEU sensitivity of the DICE flip-flop with two different layout topologies. Heavy ion experiment results indicate the separation layout topology can reduce the SEU sensitivity of the DICE flip-flop, both in SEU threshold and SEU cross section. TCAD simulation is used to investigate the mechanisms. Simulation results indicate the higher charge collection capability of adjacent transistors in the separation layout topology is the main reason to reduce the SEU sensitivity.

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Flip-flops soft error rate evaluation approach considering internal single-event transient

Abstract: Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application SCIENCE CHINA Information Sciences 55, 2390 (2012); Mirror image: newfangled cell-level layout technique for single-event transient mitigation

Cited by 15 publications

References 19 publications

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

Low power radiation aware transistor level design using tri‐state inverter embedded non‐clock gating technique

Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop

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