FlexRAM: Toward an advanced Intelligent Memory system

Yi, Kang; Huang, Wei; Yoo, Seung-Moon; Keen, Diana; Ge, Zhenzhou; Lam, Vinh Vi; Pattnaik, Pratap; Torrellas, Josep

doi:10.1109/iccd.2012.6378608

Cited by 116 publications

(72 citation statements)

References 18 publications

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“…Past work for these architectures [5,8,12,19] largely assumes that the programmer isolates the code sections to run on the memory processors. In addition, that work has mostly focused on executing sections of code on only a set of identical memory processors.…”

Section: Related Workmentioning

confidence: 99%

“…Many different types of processor in memory or intelligent memory architectures have been proposed, including IRAM [14], Shamrock [13], Raw [24], Smart Memories [16], Imagine [22], FlexRAM [12], Active Pages [19], and DIVA [8] among others. Some of these architecture projects have associated compiler efforts [1,5,8,11,18].…”

Section: Related Workmentioning

confidence: 99%

“…In this case, intelligent memory chips act as co-processors in memory that execute code when signaled by the host (main) processor. Examples of proposed systems that use this approach are Active Pages [19], DIVA [8], and FlexRAM [12].…”

Section: Introductionmentioning

confidence: 99%

“…This type of architecture, which is popularly known as intelligent memory or processor in memory, has been recently proposed for many systems [8,12,13,14,16,19,22,24].…”

Section: Introductionmentioning

confidence: 99%

“…In previous work on these systems [5,8,12,19], the programmer is expected to identify and isolate the code sections to run on the memory processors. This process is time consuming and error prone.…”

Section: Introductionmentioning

confidence: 99%

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Automatically mapping code on an intelligent memory architecture

Lee

Solihin

Torrettas³

Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture

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This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high performance with this type of architecture, code needs to be partitioned and scheduled such that each section is assigned to the processor on which it runs most efficiently. In addition, the two processors should overlap their execution as much as possible.With our algorithm, applications are mapped fully automatically using both static and dynamic information. Using a set of standard applications and a simulated architecture, we show average speedups of 1.7 for numerical applications and 1.2 for nonnumerical applications over a single host with plain memory. The speedups are very close and often higher than ideal speedups on a more expensive multiprocessor system composed of two identical host processors. Our work shows that heterogeneity can be costeffectively exploited and represents one step toward effectively mapping code on intelligent memory systems.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…This type of architecture, which is popularly known as intelligent memory or processor in memory, has been recently proposed for many systems [8,12,13,14,16,19,22,24].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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