Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits

Abstract

This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits, through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: testing a very large number of devices accurately but, also, in a timely manner. The setup consists of software and hardware components that provide a user-friendly interface to perform the statistical characterization of CMOS transistors. Five different electrical tests, comprehending time-zero and time-dependent variability effects, can be carried out. Test preparation is, with the described setup, reduced to a few seconds. Moreover, smart parallelization techniques allow reducing the typically timeconsuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology and practice of measurement of CMOS time-dependent variability, as well as the development of appropriate measurement systems and components used in efficiently generating and acquiring the necessary electrical signals.

Statistical Characterization of Time-Dependent Variability Defects Using the Maximum Current Fluctuation

“…In order to get statistically relevant data, RTN traces have been measured in 500 PMOS transistors of W/L = 80nm/60nm (integrated into an IC fabricated in a commercial 65nm planar CMOS technology specifically designed for TDV characterization) with |𝑉 | 0.1V and different gate voltages, |𝑉 | 0.6V, 0.7V, 0.8V, 1.0V and 1.2V, for 50s. Details about the IC and the measurement set-up can be found in [16] and [17]. Fig.…”

A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level

“…The setup used for the experimental characterization of the different variability phenomena discussed in this work comprises a characterization chip [8], and a dedicated, customized experimental setup [9], the schematic representation of which is depicted in Fig. 3.…”

“…In order to speed up the aging characterization tests described in Section II, a smart parallelization architecture is implemented, by means of which a large number of devices can be simultaneously stressed, while an individual transistor is being measured [9]. Appropriate scheduling of stress, measurement and stand-by periods allows the application of the same stress periods and the measurement of the same recovery phase of every device.…”

“…Such an experiment would require more than 100 days if no parallelization is implemented. With the parallelization technique presented in [9] and used in this work, the same experiment takes only 4 days.…”

“…The setup must also fulfill a set of requirements, such as the possibility of applying accurately different temperatures and voltages (accounting for the unavoidable IR drops between the chip pads and the individual device terminals), or measuring a large number (i.e., thousands) of transistors in feasible times. The first transistor array that allows the massive characterization of all phenomena, RTN, BTI, HCI and Process Variability (PV), was introduced in [8], together with a fully-customized experimental setup presented in [9]. Each sample of the characterization chip contains more than 3,000 transistors, which enables an extensive study of the variability phenomena at transistor level.…”