“…In the encoding process, the information bits are encoded and the generated parity bits are arranged into a staircase block. The resultant outer encoded bits are first interleaved by the interleaver π 1 and then de-multiplexed into T M LC = (J × D 2 )/(K pc + L 0 ) sub-blocks [7], where J, D 2 , and L 0 are the total number of staircase blocks transmitted, size of each staircase block, and the number of bits that bypass the inner SD code, respectively. Each sub-block is of size K pc + L 0 and the number of L 0 and/or K pc bits can be tuned at the de-multiplexer (DEMUX) to (i) achieve rate adaptivity with two degrees of freedom, (ii) control the amount of inner SD decoding operations and (iii) simultaneously switch between BICM (L 0 = 0) and MLC (L 0 = 0).…”