Flexible and efficient perspective transform engine

Mody, Mihir; Allu, Rajshekar; Nandan, Niraj; Hua, Gang; Sanghvi, Hetul; Dabral, Shashank; Jadav, Brijesh; Shivalingappa, Sujith; Jones, Jason

doi:10.1109/icce-asia.2017.8309322

Cited by 4 publications

(2 citation statements)

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“…Thus, it is more prudent to utilise DSP resources to implement designs based on arithmetic circuits, complexity of which is independent of the video resolution. Moreover, LUT‐based designs suffer from higher loss in result precision as noted in [21]. As discussed earlier, Simulink block also produces visually distorted output frames (Fig.…”

Section: Resultsmentioning

confidence: 91%

“…Febbo , et al [6] have proposed sub‐sampling of the software‐inspired LUT‐based approach to reduce the memory requirement and suggest using bilinear interpolation to approximate the missing values in the sub‐sampled LUT. Eo , et al [20] and Mody , et al [21] have independently described the same methodology to implement a generic perspective transform hardware engine for their respective architectures. This approach, however, does not work well for steep functions such as those for correction of very short focal length lens's distortions and leads to severe distortion in the output frame.…”

Section: Literature Reviewmentioning

confidence: 99%

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Resource‐efficient FPGA implementation of perspective transformation for bird's eye view generation using high‐level synthesis framework

Bilal

2019

IET Circuits, Devices & Systems

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Bird's eye view (BEV) generation from front-looking video stream is considered an important pre-processing task in various computer vision applications such as driver assistance systems. In this work, hardware implementation of this process using high-level synthesis in Simulink environment has been considered for rapid prototyping under real-time constraints. Traditionally, researchers have employed lookup table-based approaches to circumvent the exorbitant cost of implementing arithmetic modules associated with the perspective transformation. The hardware implementation scheme proposed here, however, demonstrates that a polynomial approximation over the limited domain of the involved operands not only saves precious hardware resources but also provides better fixed-point precision. Synthesis results on Zynq-7000 FPGA show that the proposed circuit reduces the block memory utilisation by 9% compared to the lookup table-based built-in Simulink Vision HDL block. The proposed design evaluates the results in fixed-point format which is essential for subsequent bilinear interpolation to produce high-fidelity output frame, albeit at the cost of 4% increase in DSP48E utilisation. The approximation error of the proposed solution is less than quarter-pixel on average. The proposed hardware has been integrated as an IP core in a hardware-software co-design system. The whole framework is publicly available to facilitate practitioners and researchers.

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Section: Resultsmentioning

confidence: 91%