Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime

Abstract

Abstract-With the continued scaling of NAND flash and multi-level cell technology, flash-based storage has gained widespread use in systems ranging from mobile platforms to enterprise servers. However, the robustness of NAND flash cells is an increasing concern, especially at nanometer-regime process geometries. NAND flash memory bit error rate increases exponentially with the number of program/erase cycles. Stronger error correcting codes (ECC) can be used to tolerate higher error rates, but these have diminishing returns with increasing P/E cycles and can have prohibitively high power, area, and latency overheads. The goal of this paper is to develop new techniques that can tolerate high bit error rates without requiring prohibitively strong ECC. Our techniques, called Flash Correct-and-Refresh (FCR) exploit the observation that the dominant error source in NAND flash memory is retention errors, caused by flash cells losing charge over time. The key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Detailed simulations of a solid-state drive (SSD) storage system driven by measured experimental data from error characterization on real flash memory chips show that our techniques provide 46x average lifetime improvement on a variety of workloads at no additional hardware cost. We also find that our techniques achieve lifetime improvements that cannot feasibly be achieved with stronger ECC.

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

“…One can take advantage of this in two ways: 1) keeping the strength of error correction (ECC) the same, we can have flash memory that has higher P/E cycle lifetime, 2) keeping the P/E cycle lifetime the same, we can use simpler error correction codes, which can be used to achieve the same lifetime. For example, if we apply a 32k-bit BCH code in the flash controller, the acceptable raw BER is 2x10 -3 [12] and the P/E cycle lifetimes achieved with and without read reference voltage prediction are 26k P/E cycle and 34k P/E cycles, respectively (as shown in Fig. 15).…”

“…the next 1000 P/E cycles. Note that 1000 P/E cycles equals approximately 50 days even if the disk has 20 full disk writes per day under write intensive applications [12]. This learning task can run as low priority and can be interrupted by regular I/O operations to reduce the response time penalty.…”

“…Retention errors, which occur due to flash cells gradually losing charge over time, were shown to be the dominant cause of errors in state-of-the-art MLC NAND flash memories, whereas program interference errors, which occur when the data stored in a cell/page changes unintentionally while a neighboring page is programmed, were shown to be the second dominant cause [15] [16]. Building upon this understanding, we developed techniques to reduce retention errors by adaptively refreshing and correcting flash cells [12], showing that retention errors can be effectively mitigated. Unfortunately, a detailed characterization and analysis of the second most dominant cause of errors, program interference, along with mitigation mechanisms for it, has not been provided in previous works.…”

Error Analysis and Adaptable Error-correct Scheme for NAND Flash Memory

“…Error correction methods we apply in this scheme are BCH code and FCR [9]. On consideration of hardware cost efficiency, we choose BCH code instead of LDPC code.…”

A Novel Simulation Methodology for Accelerating Reliability Assessment of SSDs

“…Also, while SSD performance can be evaluated using relatively short workload traces, accurate reliability assessments require capturing the stress-recovery patterns over an extended period of time, typically years, since endurance and retention time depends on the history of stresses and recovery over time. Existing reliability estimation approaches in the literature either merely count the number of P/E cycles [3][4], simulate the workload for only a very short interval of time, or use simplistic extrapolation of the results from a short simulation to a longer duration [5] [1]. Because reliability is affected by the interplay of the workload behavior, the flash-translation layer (FTL) algorithms for page mapping, wear-leveling, garbage collection, and the distribution of stress and recovery events, any simplistic extrapolation of a short-duration simulation over a longer timescale is inherently error-prone.…”