Fixed-Point Arithmetic Unit with a Scaling Mechanism for FPGA-Based Embedded Systems

Abstract

The work describes the new architecture of a fixed-point arithmetic unit. It is based on the use of integer arithmetic operations for which the information about the scale of the processed numbers is contained in the binary code of the arithmetic instruction being executed. Therefore, this approach is different from the typical way of implementing fixed-point operations on standard processors. The presented solution is also significantly different from the one used in floating-point arithmetic, as the decision to determine the appropriate scale is made at the stage of compiling the code and not during its execution. As a result, the real-time processing of real numbers is simplified and, therefore, faster. The described method provides a better ratio of the processing efficiency to the complexity of the digital system than other methods. In particular, the advantage of using the described method in FPGA-based embedded control systems should be indicated. Experimental tests on an industrial servo-drive confirm the correctness of the described solution.

Runtime Adaptive IoMT Node on Multi-Core Processor Platform

“…This tightly coupled hybrid architecture allows more dramatic customization and performance increase than any one implementation alone. In Reference [25], the author presents a new type of architecture based on fixed-point arithmetic. The substantial difference compared to traditional solutions is the choice of the representation scale, which in this case occurs during compilation, while in the case of floating-point arithmetic, it is performed during execution.…”

Real‐time field‐programmable gate array‐based closed‐loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia

“…The reconfigurable FPGA integrated circuit uses fixed-point computation to develop a hardware-in-the-loop realtime platform and implement bidirectional communications in animal experiments, such as brain-computer interface (BCI) systems. 12 BCI acquires physiological signals (e.g., brain signals), analyses them to extract specific features that serves as disease biomarker, and translates them into commands that control application devices like the stimulator for closed-loop deep brain stimulation. 13 BCI has been applied across diverse neurotechnological applications, playing a significant role in the development of closed-loop DBS.…”

“…Platform performance is monitored to determine real‐time computational operating speed capability. The reconfigurable FPGA integrated circuit uses fixed‐point computation to develop a hardware‐in‐the‐loop real‐time platform and implement bidirectional communications in animal experiments, such as brain‐computer interface (BCI) systems 12 . BCI acquires physiological signals (e.g., brain signals), analyses them to extract specific features that serves as disease biomarker, and translates them into commands that control application devices like the stimulator for closed‐loop deep brain stimulation 13 .…”

Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis

“…The results of restoring and non-restoring Goldschmidt division algorithms are discussed in detail. Przybyl [27] discuss the fixed-point arithmetic unit on FPGA for embedded applications with scalable features. The real-number calculation is accessible on real-time processing applications, providing faster and better processing efficiency.…”