Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs

Chen, Song; Yoshimura, Takeshi

doi:10.1109/tcad.2008.917968

Cited by 63 publications

(44 citation statements)

References 13 publications

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“…In this work, we modify the perturbation method, Insertion-afterRemove (IAR) in [2], to deal with voltage island generation during the floorplanning. The IAR perturbation method has been successfully used in multi-layer floorplanning [3].…”

Section: Methodology Flowmentioning

confidence: 99%

“…The area cost can be calculated based on W and H. The evaluation of wirelength can be done in constant time similar to that in [2]. Considering the power model defined Equation 5 and equation 1, the power of voltage island can be calculated in constant time as follows.…”

Section: Enumerating Block Positionsmentioning

confidence: 99%

“…The O(n bp ) distances x (i, j) , y (i, j) , x r (i, j) , and y r (i, j) can be computed in O(n bp ) time [2]. The evaluation of the O(n bp ) block positions can be done linearly, accordingly.…”

Section: Complexity Analysismentioning

confidence: 99%

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Practically scalable floorplanning with voltage island generation

Chen

Zhang

Yoshimura

2012

Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design

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In this paper, we propose a method of floorplanning with voltage island generation for system-on-chips (SoC) designs, which is deeply coupled with voltage island partitioning and voltage assignment, and has a good scalability. Floorplans with voltage islands are represented using nested Sequence Pairs, where the cores involved in the same voltage island consecutively appear in the sequences. Starting from a randomly generated initial floorplan, where each non chip-level core occupies an individual voltage island, we iteratively improve the solution by removing a core from the floorplan, then, inserting back the core by trying all the possible O(n 2 ) block positions, which are defined as the combinations of insertion points and voltage islands. An almost linear algorithm is devised to roughly but quickly filter many worse block positions, in each iteration, considering fixed-outline constraints, wirelength, power, power/ground routing resources, and level shifters. Compared with the latest work, the proposed method shows 9.74% and 21.04% improvements respectively on the wirelength and power when all the blocks are hard. When soft blocks are involved, the proposed method shows 12.38% wirelength reduction and 3.10% more power saving with a penalty of 7.5% whitespace. Moreover, more than 20X speedups can be obtained for the large test cases.

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Section: Methodology Flowmentioning

confidence: 99%

Section: Enumerating Block Positionsmentioning

confidence: 99%

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Practically scalable floorplanning with voltage island generation

Chen

Zhang

Yoshimura

2012

Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design

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“…Insertion after Remove (IAR) [1] is employed as the perturbation method of Simulated Annealing. The optimization flow for ISVI generation with HH method is shown in Figure 1.…”

Section: Overall Flow Of Hhmentioning

confidence: 99%

“…If ISVIs are generated, voltage islands can be constructed with more forms, which would lead to better solutions considering the power, wire, and chip area. 1 This work is partially supported by the National Natural Science Foundation of China (61404123) and the Fundamental Research Funds for the Central Universities, China (wk2100230010).…”

Section: Introductionmentioning

confidence: 99%

Irregularly shaped voltage islands generation with hazard and heal strategy

Meng¹,

Chen²,

Huang³

2015

Sixteenth International Symposium on Quality Electronic Design

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1Irregular Shaped Voltage Islands (ISVI) can achieve much better power savings in multiple supply voltage (MSV) technology. This paper proposes a simulated annealing (SA) based floorplanning method with ISVI generation using a Hazard and Heal strategy. In each perturbation of SA, a randomly chosen block is removed from floorplan and then inserted back to a proper position, to join certain voltage island. The solution space for every iteration is O(n 2 k vi ), where n is block number and k vi is voltage island number. Every position with voltage island assignment is evaluated by a linear combination of chip area, wire length, power and voltage island cost. To avoid timing-consuming evaluation of O(n 2 k vi ) possibilities, we propose a fast Hazard method to construct ISVI by skipping lots of distant voltage island candidates while occasionally accepting seldom-emerged illegal (non-contiguous) candidates. To resolve the seldom-emerged non-contiguous voltage islands, a detailed Heal method is applied in each temperature. Experimental results show the proposed method is effective and efficient compared with the latest works.

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Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

Hoo

Kanesan

Ramiah

2013

Circuit Theory & Apps

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From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two-dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference-based cost function (one-dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near-optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near-optimal outcome as compared to the other existing algorithms.

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Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs

Cited by 63 publications

References 13 publications

Practically scalable floorplanning with voltage island generation

Practically scalable floorplanning with voltage island generation

Irregularly shaped voltage islands generation with hazard and heal strategy

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

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