Five-Level Switched-Capacitor ANPC Inverter With Output Voltage Boosting Capability

Rech, Cassiano; Castiblanco, Wilmar A. P.

doi:10.1109/tie.2022.3148756

Cited by 23 publications

(6 citation statements)

References 20 publications

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“…Compared to the reverse recovery time, t r , the forward recovery time, t f , is negligible; therefore, the turn-on losses can be ignored. The turn-off losses can be calculated using Equation (22), where U rp and I rp are the reverse peak voltage and current, t b is the reverse current fall time:…”

Section: Loss Analysismentioning

confidence: 99%

“…The switching frequency is f s = 20 kHz. Based on Equation ( 9) through (22), the losses of the proposed three PDBCs and the CFLC at different output powers are calculated. According to the results of the loss calculations, the efficiency diagrams at different output power rates are generated, as shown in Figure 13.…”

Section: Loss Analysismentioning

confidence: 99%

“…However, due to the two inductance structures of the dual boost/buck converter, the volume and weight of the converter will increase. With this in mind, the multi-level dual boost/buck converter has been proposed in [16,17,22], to reduce the size and weight of this type of topology.…”

Section: Introductionmentioning

confidence: 99%

“…The bridgeless converter has a high power factor (PF), low THD and high efficiency. This type includes the basic bridgeless converters, bidirectional-switch bridgeless converters, totem pole bridgeless converters and PTP bridgeless converters [22][23][24]. Among these, the PTP bridgeless converter has a simple structure, few semiconductor devices conducting in the series loop and a natural dual-boost structure.…”

Section: Introductionmentioning

confidence: 99%

“…nics 2023, 12, x FOR PEER REVIEW 2 of 17 converters, totem pole bridgeless converters and PTP bridgeless converters [22][23][24]. Among these, the PTP bridgeless converter has a simple structure, few semiconductor devices conducting in the series loop and a natural dual-boost structure.…”

Section: Introductionmentioning

confidence: 99%

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A Family of Five-Level Pseudo-Totem Pole Dual Boost Converters

Zhao,

Miao,

Dai

et al. 2023

Electronics

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In this paper, based on the pseudo-totem pole (PTP) circuit, a family of five-level PTP dual boost converters (PDBC) is proposed. A dual boost converter has some unique advantages, such as having no risk of bridge arm shoot-through and no problems related to switch body diode reverse recovery; thus, it has a good potential for applications. First, the derivation process, working principle, modulation and strategy of the topology are analyzed. Further, the number of power devices, switch voltages and current stress of the proposed topology is analyzed. Finally, a representative five-level PDBC experimental prototype is designed with AC input 220 V/50 Hz, DC output 400 V/1 kW, and peak efficiency of 98.27%. The experimental results show that the five-level PDBC proposed in this paper has higher efficiency and the correctness of its topology is verified.

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Section: Loss Analysismentioning

confidence: 99%

Section: Loss Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Family of Five-Level Pseudo-Totem Pole Dual Boost Converters

Zhao,

Miao,

Dai

et al. 2023

Electronics

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Soft charging and fewer switches based single‐source double‐boost multilevel DC‐AC converter for low/medium voltage applications

Tiwari,

Agarwal

2024

Circuit Theory & Apps

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This paper presents a novel generalized step‐up switched‐capacitor multilevel inverter (SCMLI) appropriate for low/medium voltage input applications. To reduce the overall number of power switches, the suggested topology makes use of reduction switch count (SC) technology. The complementary working mechanism of each pair of switches simplifies the modulation method. The complete inductive‐load capability is taken into account in the proposed inverter. Furthermore, because capacitor voltages are automatically balanced, complex voltage control circuitry is not necessary. Due to a reduction in current spikes on the devices, the topology also has the ability to soft‐charge the capacitors in a quasi‐resonant manner. Performance is also enhanced by extending the lifetime and dependability of the inverters. The construction, operation, modulation method, values of the capacitors, and circuit losses are explained to demonstrate how the suggested topology should function. One of the inverter's primary differentiators from the others is its double‐boosting capability based on reduced components. Based on loss calculations, a thorough analysis of the suggested topology's efficiency of 98.31% is presented. Next, the benefits of the suggested inverter are compared to those of other inverters that have been recently suggested. The steady‐state and dynamic performance of the suggested topology is then confirmed by modeling the system on the Simulink platform and performing experiments using a DSP‐based prototype experimental setup.

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