FITTest BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties

Pecenka, T.; Kotásek, Zdenĕk; Sekanina, Lukáš

doi:10.1109/ddecs.2006.1649636

Cited by 7 publications

(5 citation statements)

References 8 publications

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“…To demonstrate that our TA methodology works, we used Cirgen [11] (described in the previous section) to design a set of structurally described RTL benchmark circuits FITTest BENCH06 [10]. The final intensions were as follows: 1) circuits with specific diagnostic properties and various structures will be evolved, 2) the circuits evolved will be analyzed by means of the methodology presented in this paper and with commercial ATPG tool, and 3) these two results will be compared.…”

Section: Resultsmentioning

confidence: 99%

“…First, both methods were compared on the set of twelve benchmark circuits from FITTest BENCH06 set [10]. The benchmark circuits on three levels of complexity (approximately 2000, 10000 a 28000 gates) were used.…”

Section: Resultsmentioning

confidence: 99%

“…The set of 20 benchmark circuits described as RTL structure were developed [10]. Each circuit is also available as gate-level structure in several formats (VHDL, Verilog, EDIF).…”

Section: Discussionmentioning

confidence: 99%

See 2 more Smart Citations

Testability Estimation Based on Controllability and Observability Parameters

Pecenka

Strnadel

Kotásek

et al. 2006

9th EUROMICRO Conference on Digital System Design (DSD'06)

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In the paper a method for estimation the circuit testability on the Register Transfer Level (RTL) is presented. The method allows to perform fast testability estimation in linear time complexity (regarding the number of components and interconnects of the circuit). Proposed approach is based on utilization of controllability and observability measurement for estimation of overall circuit testability. The application of developed method is demonstrated in a software tool for the development of RTL benchmark circuits with predefined testability properties. The resultsgained by our testability analysis method are compared with the results of professional ATPG tool. Experiments show the good correlation of the results obtained by our method and professional ATPG tool with significantly lower time complexity when our algorithm is used.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Testability Estimation Based on Controllability and Observability Parameters

Pecenka

Strnadel

Kotásek

et al. 2006

9th EUROMICRO Conference on Digital System Design (DSD'06)

Self Cite

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“…The authors released FITTest BENCH06 set, consisting of 20 synthetic sequential circuits with maximum 3,10,610 gate complexity [34]. In their subsequent paper [35], the authors illustrated a SBC generation methodology with predefined testability.…”

Section: Existing Sbc Generation Methodsmentioning

confidence: 99%

Synthetic benchmark digital circuits: A survey

Srivani¹,

Kamakoti²

2012

IETE Tech Rev

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Today's VLSI CAD tools are to be designed to handle tomorrow's designs. But, what are tomorrow's designs? How large and complex will they be? are important questions, realistic answers for which are necessary for the tool architects. The scenario is similar in the case of hardware architects including those who design processors and FPGAs. For the VLSI CAD tool and FPGA architects, the synthetic benchmark circuits (SBCs) come to their rescue by providing representative designs of tomorrow. This paper elaborates on the various techniques reported in the literature for generation of SBCs. It also presents a case study of generating a SBC for accelerated life testing of an FPGA. The paper concludes posing interesting open issues in this field.

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“…(2) The evolved circuits are the largest circuits evolved so far. The website of the FITTest BENCH06 Benchmarks project [17] shows that the most complicated benchmark circuit (s20) consists of 310,610 gates (700 components, 180 primary inputs).…”

Section: Evolution Of Benchmark Circuitsmentioning

confidence: 99%

Evolutionary Design of Digital Circuits: Where Are Current Limits?

Sekanina

2006

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)

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The objective of this paper is to classify the approaches proposed to the evolutionary digital circuit design in the recent years and to identify the levels of complexity and innovation that can be obtained by means of these approaches. In particular, gate-level evolution, circuit evolution in PLAs, functional-level evolution, incremental evolution, evolution utilizing developmental schemes and some application-specific schemes are analyzed. It is shown that we are able to effectively explore the search spaces not much larger than 2 1000 points and that the innovative solutions can be produced independently of the utilized method.

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FITTest BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties

Cited by 7 publications

References 8 publications

Testability Estimation Based on Controllability and Observability Parameters

Testability Estimation Based on Controllability and Observability Parameters

Synthetic benchmark digital circuits: A survey

Evolutionary Design of Digital Circuits: Where Are Current Limits?

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