FINN- R

Abstract

Convolutional Neural Networks have rapidly become the most successful machine-learning algorithm, enabling ubiquitous machine vision and intelligent decisions on even embedded computing systems. While the underlying arithmetic is structurally simple, compute and memory requirements are challenging. One of the promising opportunities is leveraging reduced-precision representations for inputs, activations, and model parameters. The resulting scalability in performance, power efficiency, and storage footprint provides interesting design compromises in exchange for a small reduction in accuracy. FPGAs are ideal for exploiting low-precision inference engines leveraging custom precisions to achieve the required numerical accuracy for a given application. In this article, we describe the second generation of the FINN framework, an end-to-end tool that enables design-space exploration and automates the creation of fully customized inference engines on FPGAs. Given a neural network description, the tool optimizes for given platforms, design targets, and a specific precision. We introduce formalizations of resource cost functions and performance predictions and elaborate on the optimization algorithms. Finally, we evaluate a selection of reduced precision neural networks ranging from CIFAR-10 classifiers to YOLO-based object detection on a range of platforms including PYNQ and AWS F1, demonstrating new unprecedented measured throughput at 50 TOp/s on AWS F1 and 5 TOp/s on embedded devices.

A Review of Binarized Neural Networks

“…Topology [52] 95.7 FC200-3FC100-FC10 [1] 96.0 MLP [51] 97 NK [53] 97.0 LeNet [54] 97.69 MLP [55] 97.86 ConvPool-2 [35] 98. 25 1/4 MLP [41] 98.4 MLP [56] 98.40 MLP [57] 98.6 NK [58] 98.67 MLP [59] 98.77 FC784-3FC512-FC10 Table 6.…”

“…Source Accuracy (%) Topology Precision [14] 95.15 NK Ternary values [60] 96.9 NK 8-bit values [60] 97.2 NK 12-bit values [58] 98.53 MLP 2-bits values [19] 98.71 BinaryConnect deterministic 32-bit float activations [54] 98.74 MLP 32-bit float [19] 98.82 BinaryConnect stochastic 32-bit float activations [12] 99.1 NK Ternary values Table 7. BNN accuracies on the SVHN dataset.…”

“…CPU-FPGA hybrid systems offer a CPU and FPGA connected in the same silicon. These systems are widely used to implement DNNs and BNNs [35,38,39,41,54,[61][62][63]68,71]. The CPU is flexible and easily programmed to load inputs to the DNN.…”

“…This type of work flow is called High Level Synthesis (HLS). HLS has been a major component of the research done with BNNs on FPGAs [35,[38][39][40]54,56,63,68,69,72].…”

“…The FINN tool received an extension allowing it to work with BNN topologies for LSTMs [69]. Xilinx Research labs also extended the capabilities of FINN by allowing it to work with multi-bit quantized networks, not just with BNNs [54].…”