1998
DOI: 10.1109/66.705380
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Finite element simulation of a stress history during the manufacturing process of thin film stacks in VLSI structures

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Cited by 43 publications
(13 citation statements)
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“…Thermal stress modeling of Al interconnects and its implications in their structural integrity are relatively well established. [14][15][16][17][18][19][20][21][22][23][24][25][26][27] Such is not the case for Cu-based systems. Available studies 28,29 have used simplified material or mechanical models, as will be discussed in this article.…”
Section: Introductionmentioning
confidence: 99%
“…Thermal stress modeling of Al interconnects and its implications in their structural integrity are relatively well established. [14][15][16][17][18][19][20][21][22][23][24][25][26][27] Such is not the case for Cu-based systems. Available studies 28,29 have used simplified material or mechanical models, as will be discussed in this article.…”
Section: Introductionmentioning
confidence: 99%
“…A typical manufacturing process consists of several cycles where the temperature is raised and then cooled down to room temperature. In the present simulations the film is cooled down from 600 to 300 K to simulate the level of stresses at which thin films are subjected during fabrication of microelectronics [30].…”
Section: Resultsmentioning
confidence: 99%
“…In a finite element study taking into account the stress history during device manufacturing [303], it was illustrated that the final stress state in the metal lines at room temperature resulting from the extensive thermal excursions is essentially the same as that obtained from a single-step modeling of the final cooling process. This suggests that assuming a single cooling step from a stress-free temperature is a reasonable approach to calculate thermal stresses generated in multilevel metal lines.…”
Section: Multilevel Interconnectsmentioning
confidence: 97%