FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET

“…After the ideal, non-deformed device has been calibrated to produce sound results, the GER is applied to the gate of the device. GER has been designed similarly to the line edge roughness (LER) using the Fourier synthesis methodology as previously explained in [7] [25]. To parametrize the GER, two variables have been defined: the correlation length (CL), that models the width of the Gaussian filter on the gate long edges, and the root mean square (RMS) height that quantifies the variations in the width of the gate in the transport direction.…”

“…Finally, we have compared the impact of GER (CL/Gate Perimeter = 0.66, RMS = 0.80 nm) against three of the major variability sources affecting multigate devices: MGG, LER and RD. The results for MGG (grain size = 5.0 nm) and LER (CL = 20 nm, RMS ≈ 0.80 nm) are taken from previously published DG-DD simulations [23] [25], whereas the RD variability is explicitly simulated for this study following the methodology from [29]. Fig 4 shows the impact on σV T (top) and on σlog 10 (I OFF ) (bottom) of the aforementioned four sources of variability and the combined effect of them for both the FinFET and GAA NW FET.…”

“…The GER variability for σV T is around 62% and 86% smaller for the FinFET and the GAA NW FET, respectively, than the LER variations, which is the most damaging source of variability. The LER variability is larger for the GAA NW FET than the FinFET because of its smaller channel height leading to a stronger confinement limiting the device conductivity in the transport direction [25]. Moreover, although the impact of GER on the FinFET is greater than on the GAA NW FET, the statistical combination of the four sources shows that the FinFET device is more resilient to the effect of variability (with a σV Tcomb = 30 mV and a σlog 10 (I OFFcomb ) = 0.44), a value 46% lower for σV T and 56% lower for σlog 10 (I OFF ) than that of the GAA NW FET.…”

“…GER variability for σV T (top) and σlog 10 (I OFF ) (bottom) compared to other major sources of variability (MGG[25], LER [23][25] and RD) and their combined effect (COMB) at V D,sat = 0.70 V.…”

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

“…All these short channel effects could be suppressed by changing the device structure from planar MOSFETs to FinFETs [49] and gate-all-around (GAA) FETs [50]. The FinFETs have become the mainstream logic devices for a few nodes [51].…”