FineReg: Fine-Grained Register File Management for Augmenting GPU Throughput

Oh, Yunho; Yoon, Myung Kuk; Song, Won Kyung; Ro, Won Woo

doi:10.1109/micro.2018.00037

Cited by 11 publications

(6 citation statements)

References 32 publications

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“…GPUs have dozens of SMs, and the TB scheduler assigns TBs to SMs based on the scheduling policy. The number of assigned TBs is determined by thread count limit, shared memory size, and register file size [20], [25], [26].…”

Section: B Baseline Gpu Architecturementioning

confidence: 99%

“…Three factors determine the number of threads that can be scheduled on SMs: the size of register file, the size of shared memory, and the maximum thread count limit [20], [25], [26]. TBs are scheduled on SMs until reaching one of the limitations.…”

Section: Thread Context-aware Register Cachementioning

confidence: 99%

“…The latest generation of NVIDIA GPU architecture, Ampere (A100), can schedule up to 221,184 (2,048×108) threads concurrently and has 27,648 KB (256 KB×108) register file to hold the contexts of such threads [6]. Compared to the previous generation, Volta (V100), the Ampere architecture has 25.9% (20,480 KB vs. 27,647 KB) larger register file and can schedule up to 25.9% (163,840 vs. 221,184) more threads [6], [7]. A similar trend has been observed across several previous GPU architecture generations [8].…”

Section: Introductionmentioning

confidence: 99%

“…In GPUs, there is a strong correlation between the number of registers used by each warp and the number of warps scheduled on SMs. The register file size is one major factor that determines the number of issuable warps in GPUs [20]. As the number of registers used by a warp increases, the number of warps scheduled on SMs is decreased and vice versa.…”

Section: Introductionmentioning

confidence: 99%

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TEA-RC: Thread Context-Aware Register Cache for GPUs

Jeong

et al. 2022

IEEE Access

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Graphics processing units (GPUs) achieve high throughput by exploiting a high degree of thread-level parallelism (TLP). To support such high TLP, GPUs have a large-sized register file to store the context of all threads, consuming around 20% of total GPU energy. Several previous studies have attempted to minimize the energy consumption of the register file by implementing an emerging non-volatile memory (NVM), leveraging its higher density and lower leakage power over SRAMs. To amortize the cost of long access latency of NVM, prior work adopts a hierarchical register file consisting of an SRAM-based register cache and an NVM-based registers where the register cache works as a write buffer. To get the register cache index, they use the partially selected bits of warp ID and register ID. This work observes that such an index calculation causes three types of contentions leading to the underutilization of the register cache: inter-warp, intra-warp, and false contentions. To minimize such contentions, this paper proposes a thread contextaware register cache (TEA-RC) in GPUs. In TEA-RC, the cache index is calculated considering the high correlation between the number of scheduled threads and the register usage of threads. The proposed design shows 28.5% higher performance and 9.1 percentage point lower energy consumption over the conventional register cache that concatenates three bits of warp ID and five bits of register ID to compute the cache index.INDEX TERMS Graphics processing units; register file; register cache; volatile memory; non-volatile memory, hybrid register file, hierarchical register file This article has been accepted for publication in IEEE Access.

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Section: B Baseline Gpu Architecturementioning

confidence: 99%

Section: Thread Context-aware Register Cachementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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TEA-RC: Thread Context-Aware Register Cache for GPUs

Jeong

et al. 2022

IEEE Access

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“…RegMutex [25] improved performance by sharing a subset of physical registers between warps during the GPU kernel execution. FineReg [42] achieved a higher number of concurrent CTAs by partitioning the register ile into two regions, one for active CTAs and another for pending CTAs. Register ile slicing [20] proposed to split the data path into two 16-bit slices, which enables the register to save power by power gating a slice if storing narrow-values, or to improve performance by fetching two 16-bit values.…”

Section: Related Workmentioning

confidence: 99%

Corf

Esfeden

Khorasani

Jeon

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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The Register File (RF) in GPUs is a critical structure that maintains the state for thousands of threads that support the GPU processing model. The RF organization substantially afects the overall performance and the energy eiciency of a GPU. For example, the frequent accesses to the RF consume a substantial amount of the dynamic energy, and port contention due to limited ports on operand collectors and register ile banks afect performance as register operations are serialized. We present CORF, a compiler-assisted Coalescing Operand Register File which performs register coalescing by combining reads to multiple registers required by a single instruction, into a single physical read. To enable register coalescing, CORF utilizes register packing to co-locate narrow-width operands in the same physical register. CORF uses compiler hints to identify which register pairs are commonly accessed together. CORF saves dynamic energy by reducing the number of physical register ile accesses, and improves performance by combining read operations, as well as by reducing pressure on the register ile. To increase the coalescing opportunities, we re-architect the physical register ile to allow coalescing reads across diferent physical registers that reside in mutually exclusive sub-banks; we call this design CORF++. The compiler analysis for register allocation for CORF++ becomes a form of graph coloring called the bipartite edge frustration problem. CORF++ reduces the dynamic energy of the RF by 17%, and improves IPC by 9%.

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Virtual-Cache: A cache-line borrowing technique for efficient GPU cache architectures

Jiang

Kim

2021

Microprocessors and Microsystems

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FineReg: Fine-Grained Register File Management for Augmenting GPU Throughput

Cited by 11 publications

References 32 publications

TEA-RC: Thread Context-Aware Register Cache for GPUs

TEA-RC: Thread Context-Aware Register Cache for GPUs

Corf

Virtual-Cache: A cache-line borrowing technique for efficient GPU cache architectures

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