Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

Abstract

In this paper, we present a relatively primitive execution model for ne-grain parallelism, in which all synchronization, scheduling, and storage management is explicit and under compiler control. This is dened by a threaded abstract machine (TAM) with a multilevel scheduling hierarchy. Considerable temporal locality of logically related threads is demonstrated, providing an avenue for eective register use under quasi-dynamic scheduling.A prototype TAM instruction set, TL0, has been developed, along with a translator to a variety of existing sequential and parallel machines. Compilation of Id, an extended functional language requiring ne-grain synchronization, under this model yields performance approaching that of conventional languages on current uniprocessors.Measurements suggest that the net cost of synchronization on conventional multiprocessors can be reduced to within a small factor of that on machines with elaborate hardware support, such as proposed dataow architectures. This brings into question whether tolerance to latency and inexpensive synchronization require specic hardware support or merely an appropriate compilation strategy and program representation.

Apple-CORE: Microgrids of SVP Cores -- Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management

“…This idea to introduce hardware support for concurrency management is not new [12], [17], [18], [19], [20]; however previous research met with resistance against the introduction of explicit concurrency in applications. Now that on-chip software concurrency is the norm, hardware support deserves renewed attention for two reasons.…”

The Sisal model of functional programming and its implementation

“…The Frame model is used in several multithreaded machines (e.g. TAM [12], StarT-NG [4] and the EM4 and EM-X [20]). When an instance of a particular code-block is invoked, a frame is first allocated in a given processor's frame store and all the tokens generated within that codeblock instance will be stored in that frame.…”

“…New architectures such as E R A [3] and *T [26] are being built with hardware support for multithreading. In aiddition, software multithreading models such as TAM [12] and MIDC [7]), are being investigated.…”

An executable analytical performance evaluation approach for early performance prediction

“…In a single-threaded execution model, during this long-latency, the processor idles, waiting for the data to arrive from lower levels in the memory hierarchy. In a threaded execution, if the long-latency operation is split across two threads (as in a split-phase read [11,7,10]), then the processor switches context during the long latency and executes other useful work. The data to be percolated is identified either by the compiler or by the programmer.…”

“…A number of multithreaded architecture designs have been reported in the literature [2,4,7,10,11,16,18]. The performance of multithreaded multiprocessor systems have been studied through an analytical approach by Agarwal [1], Alkalaj and Bopanna [3], Boothe and Ranade [5], Nemawarkar and Gao [14], Nemawarkar, et al [15], and Saavedra-Barrera, et al [17].…”