Fine-Grain Dynamic Energy Tracking for System on Chip

Mansouri, Imen; Benoit, Pascal; Torres, Lionel; Clermidy, Fabien

doi:10.1109/tcsii.2013.2258246

Cited by 3 publications

(5 citation statements)

References 9 publications

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“…Table V compares the error of the three models using six signals (the highest accuracy achieved) with the previously presented works that only consider the variation of the activity in their models. The most similar approaches are the ones that appraise the system activity using the toggling information with a linear model at the hardware level [16], [17]. The obtained average error in [16] for the small circuits (RAM and DSP) is about 7% at the resolution of 100 μs, while in [17] 2.5% of average error was achieved using nine signals for also small components such as a divider, a multiplier and an instruction/data caches.…”

Section: F Results Analysismentioning

confidence: 99%

“…The most similar approaches are the ones that appraise the system activity using the toggling information with a linear model at the hardware level [16], [17]. The obtained average error in [16] for the small circuits (RAM and DSP) is about 7% at the resolution of 100 μs, while in [17] 2.5% of average error was achieved using nine signals for also small components such as a divider, a multiplier and an instruction/data caches. Our obtained average error is much lower compared to [16] at the same granularity, and is comparable to [17] with a lower overhead as the number of signals used in our linear model is lower (6 in this case).…”

Section: F Results Analysismentioning

confidence: 99%

“…However, there exist also several works that use the toggling information at hardware level to estimate the activity factor α. A technique based on hidden Markov models is proposed in [16] to track at run-time the system power modes. Power variations are represented as a fix number of power modes depending on the activity of strategic nets chosen at the register transfer (RT)-level.…”

Section: Background and Related Workmentioning

confidence: 99%

“…From the variety of approaches in the literature, it is clear that current solutions are either imprecise or too design and technology specific. Our estimation method relies on the information at the hardware level, which compared to existing hardware-level methods [16], [17], is a systematic and generic approach addressing complex systems and can be applied to any circuit and any technology. In our method, the global activity is appraised from the toggling activity on few strategic signals at the RT-level.…”

Section: Background and Related Workmentioning

confidence: 99%

See 3 more Smart Citations

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

Najem

Benoit

Ahmad

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The emergence of power as a first-class design constraint has fueled the proposal of a growing number of optimization techniques, seeking the best tradeoff to reach the maximum energy efficiency. Effective adaptation strategies depend critically on the monitoring method as an incorrect assessment of the system's state will result in poor decision making. Yet it is indeed a fundamental issue: how to get a precise estimation of the system's state, and especially in a cost-effective way? We address this question for the self-observation of the power consumption. We develop a method that combines several data mining algorithms to monitor the toggling activity on a few relevant signals selected at the register transfer-level. Our approach is based on a generic flow that is able to produce a power model for any register transfer level (RTL) circuit on any technology. This contribution is evaluated on a system on chip RTL model implemented on an field-programmable gate array technology. The experiments demonstrate that the proposed method achieves the accuracy of analog power sensors (error lower than 1%) at a finer granularity and in a cost-effective way. Index Terms-Data mining, design-time method, fieldprogrammable gate array (FPGA), power modeling, register transfer-level, system on chip (SoC) monitoring.

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Section: F Results Analysismentioning

confidence: 99%

Section: F Results Analysismentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

See 2 more Smart Citations

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

Najem

Benoit

Ahmad

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…The authors use data read miss and write miss to estimate the dynamic power for an interconnect component. Another approach based on Hidden Markov Models has been proposed in [10] to track at run-time the system power modes.…”

Section: Power Modeling Flowmentioning

confidence: 99%

Method for dynamic power monitoring on FPGAs

Najem

Benoit

Bruguier

et al. 2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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The ever-increasing integration densities make it possible to configure multi-core systems composed of hundreds of blocks on existing FPGAs that may influence overall consumption differently. Observing total consumption is not sufficient to accurately assess internal circuit activity to be able to deploy effective adaptation strategies. In this case monitoring techniques are required. This paper presents a CAD flow for high-level dynamic power estimation on FPGAs. The method is based on the monitoring of toggling activity for relevant signals by introducing event counters. The appropriate signals are selected using the Greedy Stepwise filter. Our approach is based on a generic method that is able to produce a power model for any block-based circuit. We evaluated our contribution on a SoC RTL model implemented on Spartan3, Virtex5, and Spartan6 FPGAs. A power model and monitors are automatically generated to achieve the best tradeoff between accuracy and overhead.

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Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing

Akgul

Puschini

Lesecq

et al. 2013

2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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International audienceEmbedded systems need ever increasing computational performances. Since they have limited energy resources, power consumption has to be minimized. Dynamic Voltage and Frequency Scaling (DVFS) techniques combined with Body Biasing techniques decrease the power consumption of a chip by providing just enough computational performance to the chip so as to finish the task at its deadline. A Power Mode (PM) is defined with the clock frequency F applied to the chip and the power P consumed by the chip. Executing tasks with the 2 neighbor frequencies of the target frequency should minimize the power consumption. Unfortunately, this choice is not always optimal since the set of available PMs may not fulfil the convexity property anymore when 3 actuators are considered. Here, a method is proposed to tackle this issue. PMs are selected to form a discretely convex subset. Results for a ring oscillator in FD-SOI exemplify that the proposed approach can save power consumption

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Fine-Grain Dynamic Energy Tracking for System on Chip

Cited by 3 publications

References 9 publications

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

Method for dynamic power monitoring on FPGAs

Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing

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